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74LVC1G175DCKRG4 数据表(PDF) 11 Page - Texas Instruments |
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74LVC1G175DCKRG4 数据表(HTML) 11 Page - Texas Instruments |
11 / 28 page SN74LVC1G175 GND D VCC = 5 V CLK Q VCC Serial Input Data Clock Pulse SN74LVC1G175 GND D CLK Q VCC SN74LVC1G175 GND D CLK Q VCC SN74LVC1G175 GND D CLK Q VCC Serial Output Dat a A B C D SN74LVC1G175 www.ti.com SCES560G – MARCH 2004 – REVISED JUNE 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information Multiple SN74LVC1G175 devices can be used in tandem to create a shift register of arbitrary length. In this example, we use four SN74LVC1G175 devices to form a 4-bit serial shift register. By connecting all CLK inputs to a common clock pulse and tying each output of one device to the next, we can store and load 4-bit values on demand. We demonstrate loading the 4 bit value 1101 into memory by setting Serial Input Data to each desired memory bit, and by sending a clock pulse for each bit, we sequentially move all stored bits from left to right (A → B → C → D) 9.2 Typical Application Figure 4. 4-Bit Serial Shift Register Table 2. Stored Data Values Serial Input Data Stored A Stored B Stored C Stored D 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 9.2.1 Design Requirements The SN74LVC1G175 device uses CMOS technology and has balanced output drive. Care must be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The SN74LVC1G175 allows storing digital signals with a digital control signal. All input signals should remain as close as possible to either 0 V or VCC for optimal operation. 9.2.2 Detailed Design Procedure 1. Recommended input conditions: – For rise time and fall time specifications, see Δt/Δv in the table. – For specified high and low levels, see VIH and VIL in the table. – Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC. 2. Recommended output conditions: – Load currents should not exceed ±50 mA. Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: SN74LVC1G175 |
类似零件编号 - 74LVC1G175DCKRG4 |
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类似说明 - 74LVC1G175DCKRG4 |
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