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74AHCT1G125DCKTE4 数据表(PDF) 8 Page - Texas Instruments |
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74AHCT1G125DCKTE4 数据表(HTML) 8 Page - Texas Instruments |
8 / 22 page A Y OE 8 SN74AHCT1G125 SCLS378N – AUGUST 1997 – REVISED JANUARY 2016 www.ti.com Product Folder Links: SN74AHCT1G125 Submit Documentation Feedback Copyright © 1997–2016, Texas Instruments Incorporated 9 Detailed Description 9.1 Overview The SN74AHCT1G125 device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, data is passed from the A input to the Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 9.2 Functional Block Diagram Figure 3. Logic Diagram (Positive Logic) 9.3 Feature Description • TTL inputs – Lowered switching threshold allows up translation 3.3 V to 5 V • Slow edges reduce output ringing 9.4 Device Functional Modes Table 1. Function Table INPUTS OUTPUT Y OE A L H H L L L H X Z |
类似零件编号 - 74AHCT1G125DCKTE4 |
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类似说明 - 74AHCT1G125DCKTE4 |
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