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TPL5111EVM 数据表(PDF) 3 Page - Texas Instruments |
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TPL5111EVM 数据表(HTML) 3 Page - Texas Instruments |
3 / 21 page Normal operation I_SEL TPL5111 Current measurement I_SEL www.ti.com Setup The EVM contains one TPL5111 timer and one TPS61029 boost converter (See Table 1). Table 1. Device and Package Configurations DEVICE IC PACKAGE U1 TPL5111DDC SOT23-6 U2 TPS61029 VSON(10) 2 Setup This section describes the jumpers and connectors on the EVM as well and how to properly connect, set up and use the TPL5111EVM. Input/Output Connector Descriptions Name Layer Description J1/J3 Bottom 2 x 10 pin receptacle to plug the TPL5111EVM into MSP430F5529 Launchpad. J4/J2 Bottom 2 x 10 pin receptacle to plug the TPL5111EVM into MSP430F5529 Launchpad. RST Bottom 2 pin receptacle to plug the TPL5111EVM into MSP430F5529 Launchpad. VCC Bottom 2 pin receptacle to plug the TPL5111EVM into MSP430F5529 Launchpad. IO Top 4-pin header connector to bring out VDD_uC, DRVn, DONE and GND signals. Jumper Description Name Layer Description I_SEL Top The jumper should be installed for normal operation. Remove the jumper and connect a DMM to the terminal pins to measure current. Figure 2. I_SEL Jumper Setting Table 2. Switch Descriptions Name Layer Description S_ON_OFF Bottom The S_ON_OFF switch ensures that only one voltage source is driving the internal power buses. The common pin (Pin 2) of the switch is directly connected to the input of the TPS61029. V_BATT position selects an installed battery as the voltage source for the board functions. The AUX_VDD position selects the source attached to the AUX_VDD terminal as the voltage source for the board functions. MODE_SW Bottom TIMER position (VDD) selects the TIMER mode of operation for the TPL5111. The ONE_SHOT position (GND) selects the ONE SHOT mode of operation for the TPL5111. DONE Top SPST switch. Generates a DONE pulse when pressed. M_DRV Top SPST switch. When pressed, connects VDD to the DELAY/M_DRV pin to simulate a manual Power ON input to the TPL5111. Test Point Descriptions Name Layer Description GND Layer 2 Ground (GND) test point. V_BATT Layer 3 Battery voltage test point AUX_VDD Layer 3 Connection for external voltage source 3 SNAU183 – July 2015 TPL5111EVM User 's Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated |
类似零件编号 - TPL5111EVM |
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类似说明 - TPL5111EVM |
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