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SI4710-B30 数据表(PDF) 11 Page - Silicon Laboratories |
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SI4710-B30 数据表(HTML) 11 Page - Silicon Laboratories |
11 / 40 page Si4710/11-B30 Rev. 1.1 11 Figure 8. Digital Audio Interface Timing Parameters, I2S Mode Table 8. Digital Audio Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA =–20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit DCLK pulse width high tDCH 10 — — ns DCLK pulse width low tDCL 10 — — ns DFS set-up time to DCLK rising edge tSU:DFS 5— — ns DFS hold time from DCLK rising edge tHD:DFS 5— — ns DIN set-up time from DCLK rising edge tSU:DIN 5— — ns DIN hold time from DCLK rising edge tHD:DIN 5— — ns DCLK, DFS, DIN, Rise/Fall time tR tF — — 10 ns DCLK Tx Frequency1,2 1.0 — 40.0 MHz Notes: 1. Guaranteed by characterization. 2. The DCLK frequency may be set below the minimum specification if DIGITAL_INPUT_SAMPLE_RATE is first set to 0 (disable). DCLK DFS DIN tSU:DIN tSU:DFS tHD:DIN tHD:DFS tF tR |
类似零件编号 - SI4710-B30 |
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类似说明 - SI4710-B30 |
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