Si4708/09-C

8

Rev. 1.2

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK Frequency

0—

400

kHz

SCLK Low Time

1.3

—

—

µs

SCLK High Time

0.6

—

—

µs

SCLK Input to SDIO

(START)

0.6

—

—

µs

SCLK Input to SDIO

0.6

—

—

µs

SDIO Input to SCLK

100

—

—

ns

SDIO Input to SCLK

0—

900

ns

SCLK input to SDIO

SU:STO

0.6

—

—

µs

STOP to START Time

1.3

—

—

µs

SDIO Output Fall Time

—250

ns

SDIO Input, SCLK Rise/Fall Time

—300

ns

SCLK, SDIO Capacitive Loading

——

50

pF

Input Filter Pulse Suppression

—

—

50

ns

Notes:

2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high

until after the 1st start condition.

3. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

so long as all other timing parameters are met.