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SI4742 数据表(PDF) 8 Page - Silicon Laboratories |
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SI4742 数据表(HTML) 8 Page - Silicon Laboratories |
8 / 20 page AN400 8 Rev. 0.5 Figure 3. Layout Example 2 Place a ground plane under the Si474x as shown in Figure 4. For designs in which a continuous ground plane is not possible, place a local ground plane directly under the Si474x. Do not route signal traces on the ground layer under the Si474x. Flood the primary layer with ground, and place stitching VIAs to create a low-impedance connection between planes. If the design is sufficiently flexible to have more than two layers, put the GND plane between RF signals and digital signals. Another improvement would be to put the digital signals between two GND planes. Do not route digital or RF traces over breaks in the ground plane. Route all traces to minimize inductive and capacitive coupling by keeping digital traces away from analog and RF traces, minimizing trace length, minimizing parallel trace runs, and keeping current loops small. In particular, care should be taken to avoid routing digital signals or reference clock traces near or parallel to VCO pins 22 and 23 or LOUT/ROUT pins 15 and 16. Route digital traces on the opposite side of the chip. This means that, for a two-sided board, all RF signals should be routed on layer 1, and all digital signals should be routed on layer 2. Route digital traces including I2C and digital audio away and orthogonal to the RF traces to avoid coupling of digital noise to RF traces. This is especially important for the AM band where digital noise frequencies can easily occur. Route all GND (including RFGND) pins to the ground pad. The ground pad should be connected to the ground plane using multiple vias to minimize ground potential differences. Route power to the Si474x by trace, ensuring that each trace is rated to handle the required current. Some trace impedance is preferable so that the decoupling currents are forced to flow through decoupling caps C1, C6, C13, C17, C18, and C19 directly to the ground pins and not by alternate pathways. Place the Si474x close to the antenna(s) to minimize antenna trace length and capacitance and inductive and capacitive coupling. This recommendation must be followed for optimal device performance. Route the antenna trace over an unobstructed ground plane to minimize antenna loop area and inductive coupling. Design, place, and route other circuits such that radiation in the band of interest is minimized. Figure 4. Two-Layer Stackup p |
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类似说明 - SI4742 |
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