AN349

Rev. 0.1

9

Figure 4. Powerup Timing

Table 4 shows the sequence of commands required to powerdown the device. The tuner can optionally be

programmed to place the audio output pins into a high impedance state. If this is desired, set the AHIZEN bit in

register 07h prior to setting the disable bit. See AN230, Section "3.2.3.AHIZEN (07h.14)—Audio High-Z Enable" on

page 10 for more information. Set Register 4 [5:4] and [1:0] to 10b prior to setting the disable bit.

Table 3. Powerup Configuration Sequence

Write address 02h (required).

Example: Write data 4001h.

Wait for device powerup (required).

Read addresses 00h–01h (optional).

DEV = 0010 after powerup = Si4708.

DEV = 1010 after powerup = Si4709.

Read addresses 02h-0Fh (optional)

and to reduce the number of reads/writes to the I/O bus. These are referred to as the shadow registers and can

be stored in a 16 word array, shadow_reg[].

Example: To write bit 15 of register 07h after power up, write 07h as shadow_reg[0x07] ^ 0x8000

Write remaining hardware configuration registers (required).

Write the general configuration registers (required).

Write the regional configuration registers (required).

These registers can be programmed in any order.

WR02

RD01

ENABLE = 1

DISABLE = 0

DEV = ?

Optional

Required

See Powerup Time in data sheet

RD02-0F