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SL23EP08 数据表(PDF) 8 Page - Silicon Laboratories

部件名 SL23EP08
功能描述  Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

SL23EP08 数据表(HTML) 8 Page - Silicon Laboratories

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Rev 1.0, May 18, 2006
Page 8 of 15
SL23EP08
AC Electrical Specifications: VDD=3.3V+/-10% and -40°C to +85°C Operation (Industrial Grade)
Symbol Description
Condition
Min
Typ
Max
Unit
FOUT-1
Output Frequency
CL=30pf, All devices
10
-
160
MHz
FOUT-2
Output Frequency
CL=20pF, -1H and -5H versions
10
-
220
MHz
FOUT-2
Output Frequency
CL=15pF, -1,-2,-3 and -4 versions
10
-
200
MHz
DC-1
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=30pF, FOUT=66.6MHz and Measured
at VD/2
40.0
50.0
60.0
%
DC-2
Duty Cycle, -1, -2, -3,-4,-1H
and -5H versions
CL=15pF, FOUT<66.6MHz and Measured
at VDD/2
45.0
50.0
55.0
%
DC-1
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=30pF, FOUT=120MHz and Measured
at VDD/2
TBD
TBD
TBD
%
DC-2
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
CL=15pF, FOUT=120MHz and Measured
at VDD/2
TBD
TBD
TBD
%
tr/f-1
Rise and Fall Times. -1, -2, -
3, and -4 versions
Measured between 0.8V and 2.0V
CL=30pF
-
-
1.6
ns
tr/f-2
Rise and Fall Times. -1, -2, -
3, and -4 versions
Measured between 0.8V and 2.0V
CL=15pF
-
-
1.2
ns
tr/f-3
Rise and Fall Times. -1,1H
and -5H versions
Measured between 0.8V and 2.0V
CL=30pF
-
-
1.2
ns
tr/f-3
Rise and Fall Times. -1H and
-5H versions
Measured between 0.8V and 2.0V
CL=15pF
-
-
1.0
ns
SKW-1
Output-to-Output on same
bank A or B. All versions
All outputs are equally loaded. Measured
at VDD/2
-
60
150
ps
SKW-2
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
All outputs are equally loaded. Measured
at VDD/2
-
60
150
ps
SKW-3
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
All outputs are equally loaded. Measured
at VDD/2
-
130
300
ps
SKW-4
Device-to-Device Skew.
All versions
All outputs are equally loaded. Measured
at VDD/2 and FBK pin
-
180
500
ps
tCFD
CLKIN to FBK Rising Edge
Delay
All outputs are equally loaded. Measured
at VDD/2
-200
-
200
ps
t2
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
Edge
(Measured at VDD/2)
[2]
PLL Bypass mode
1.5
4.4
ns
PLL enabled @ 3.3V
–100
100
ps
PLL enabled @2.5V
–200
200
ps
t3
Part-to-Part Skew
[2]
(Measured at VDD/2)
Measured at VDD/2. Any output to any
output, 3.3V supply
±150
ps
Measured at VDD/2. Any output to any
output, 2.5V supply
±300
ps
tLOCK
PLL Lock Time
Valid on all clock pins from VDD=2.97V
-
-
1.0
ms


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