数据搜索系统,热门电子元器件搜索 |
|
SI53360 数据表(PDF) 8 Page - Silicon Laboratories |
|
SI53360 数据表(HTML) 8 Page - Silicon Laboratories |
8 / 15 page Si53360 8 Rev. 1.1 3. Pin Description: 16-TSSOP Table 9. Si53360 Pin Description* Pin # Name Type* Description 1 OE I Output enable. When OE= high, the clock outputs are enabled. When OE= low, the clock outputs are tri-stated. OE features an internal pull-up resistor, and may be left unconnected. 2VDD P Core voltage supply. Bypass with 1.0 F capacitor and place as close to the VDD pin as possible. 3 Q0 O Output clock 0. 4 Q1 O Output clock 1. 5 Q2 O Output clock 2. 6 Q3 O Output clock 3. 7 GND GND Ground. 8 CLK0 I Input clock 0. 9 CLK1 I Input clock 1. 10 GND GND Ground. 11 Q4 O Output clock 4. 12 Q5 O Output clock 5. 13 Q6 O Output clock 6. 14 Q7 O Output clock 7. *Note: Pin types are: I = input, O = output, P = power, GND = ground. CLK_SEL VDD Q7 Q6 Q5 Q4 CLK1 OE VDD Q0 Q1 Q2 Q3 CLK0 GND GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 |
类似零件编号 - SI53360 |
|
类似说明 - SI53360 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |