Si7006-A20

6

Rev. 1.1

Stop Setup Time

0.6

—

—

μs

Bus Free Time

Between Stop and Start

1.3

—

—

μs

SDA Setup Time

100

—

—

ns

SDA Hold Time

100

—

—

ns

SDA Valid Time

—

—

0.9

μs

SDA Acknowledge Valid Time

—

—

0.9

μs

Suppressed Pulse Width3

50

—

—

ns

1.9

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

2. Depending on the conversion command, the Si7006 may hold the master during the conversion (clock stretch). At

above 100 kHz SCL, the Si7006 may also hold the master briefly for user register and device ID transactions. At the

3. Pulses up to and including 50 ns will be suppressed.