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SI599 数据表(PDF) 8 Page - Silicon Laboratories |
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SI599 数据表(HTML) 8 Page - Silicon Laboratories |
8 / 28 page Si598/Si599 8 Rev. 1.0 Table 5. CLK± Output Phase Jitter (Si598) (Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Units Phase Jitter (RMS Random) 12 kHz to 20 MHz Integration Bandwidth φJ-RANDOM LVPECL/LVDS/CML1 —0.5 — ps CMOS 3.3 V2 —0.6 — ps Phase Jitter (RMS Random) 1.875 to 20 MHz Integration Bandwidth LVPECL/LVDS/CML1 —0.3 — ps CMOS 3.3 V2 —0.5 — ps Phase Jitter (RMS) 12 kHz to 20 MHz Integration Bandwidth φJ LVPECL/LVDS/CML1 —0.5 1 ps CMOS 3.3 V2 —0.6 1 ps Phase Jitter (RMS) 1.875 to 20 MHz Integration Bandwidth LVPECL/LVDS/CML1 —0.5 — ps CMOS 3.3 V2 —0.5 — ps Notes: 1. 50 to 810 MHz, 3.3 V/2.5 V only. 2. 50 to 160 MHz, single-ended CMOS output phase jitter measured using 33 series termination into 50 phase noise test equipment. 3.3 V supply voltage option only. Table 6. CLK± Output Phase Jitter (Si599) (Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Units Phase Jitter (RMS)1,2 for FOUT of 50 MHz < FOUT 810 MHz J Kv = 45 ppm/V 12 kHz to 20 MHz — 0.5 — ps Kv = 95 ppm/V 12 kHz to 20 MHz — 0.5 — ps Kv = 125 ppm/V 12 kHz to 20 MHz — 0.5 — ps Kv = 185 ppm/V 12 kHz to 20 MHz — 0.5 — ps Kv = 380 ppm/V 12 kHz to 20 MHz — 0.7 — ps Notes: 1. Differential Modes: LVPECL/LVDS/CML. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. |
类似零件编号 - SI599 |
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类似说明 - SI599 |
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