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TPA6166A2YFFR 数据表(PDF) 8 Page - Texas Instruments |
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TPA6166A2YFFR 数据表(HTML) 8 Page - Texas Instruments |
8 / 49 page SCL SDA t h2 t (buf) t su2 t su3 Start Condition Stop Condition T0028-01 SCL SDA t w(H) t w(L) t su1 t h1 T0027-02 TPA6166A2 SLAS997B – MARCH 2014 – REVISED JANUARY 2015 www.ti.com 6.8 Timing Requirements For I 2C interface signals and voltage power-up sequence, over recommended operating conditions (unless otherwise noted). Timing is specified by design. MIN MAX UNIT fSCL Frequency, SCL No wait states 400 kHz tw(H) Pulse duration, SCL high 0.6 μs tw(L) Pulse duration, SCL low 1.3 μs tsu1 Setup time, SDA to SCL 100 ns th1 Hold time, SCL to SDA 10 ns t(buf) Bus free time between stop and start condition 1.3 μs tsu2 Setup time, SCL to start condition 0.6 μs th2 Hold time, start condition to SCL 0.6 μs tsu3 Setup time, SCL to stop condition 0.6 μs tSP Pulse width of surpressed spike 0 50 ns Figure 1. SCL and SDA Timing Figure 2. Start and Stop Conditions Timing 8 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPA6166A2 |
类似零件编号 - TPA6166A2YFFR |
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类似说明 - TPA6166A2YFFR |
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