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54ABT652J-QML 数据表(PDF) 3 Page - National Semiconductor (TI) |
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54ABT652J-QML 数据表(HTML) 3 Page - National Semiconductor (TI) |
3 / 17 page Pin Descriptions Pin Names Description A 0–A7 Data Register A Inputs/TRI-STATE Outputs B 0–B7 Data Register B Inputs/TRI-STATE Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Select Inputs OEAB, OEBA Output Enable Inputs Logic Diagram Functional Description In the transceiver mode, data present at the HIGH imped- ance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the ’ABT652C. Data on the A or B data bus, or both can be stored in the in- ternal D flip-flop by LOW to HIGH transitions at the appropri- ate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output rein- forces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. DS100220-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.national.com |
类似零件编号 - 54ABT652J-QML |
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类似说明 - 54ABT652J-QML |
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