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CS5336-BP 数据表(PDF) 4 Page - Cirrus Logic |
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CS5336-BP 数据表(HTML) 4 Page - Cirrus Logic |
4 / 34 page Parameter Symbol Min Typ Max Unit ICLKD Period (CMODE low) (Note 6) t clkw1 78 - 3906 ns ICLKD Low (CMODE low) t clkl1 31 - - ns ICLKD High (CMODE low) t clkh1 31 - - ns ICLKD rising to OCLKD rising (CMODE low) t io1 5 - 40 ns ICLKD Period (CMODE high) t clkw2 52 - 2604 ns ICLKD Low (CMODE high) t clkl2 20 - - ns ICLKD High (CMODE high) t clkh2 20 - - ns ICLKD rising or falling to OCLKD rising (CMODE high, Note 4) t io2 5 - 45 ns ICLKD rising to L/R edge (CMODE low, MASTER mode) t ilr1 5 - 50 ns ICLKD rising to FSYNC edge (CMODE low, MASTER mode) t ifs1 5 - 50 ns ICLKD rising to SCLK edge (CMODE low, MASTER mode) t isclk1 5 - 50 ns ICLKD falling to L/R edge (CMODE high, MASTER mode) t ilr2 5 - 50 ns ICLKD falling to FSYNC edge (CMODE high, MASTER mode) t ifs2 5 - 50 ns ICLKD falling to SCLK edge (CMODE high, MASTER mode) t isclk2 5 - 50 ns SCLK rising to SDATA valid (MASTER mode, Note 5) t sdo 0 - 50 ns SCLK duty cycle (MASTER mode) 40 50 60 % SCLK rising to L/R (MASTER mode, Note 5) t mslr -20 - 20 ns SCLK rising to FSYNC (MASTER mode, Note 5) t msfs -20 - 20 ns SCLK Period (SLAVE mode) t sclkw 155 - - ns SCLK Pulse Width Low (SLAVE mode) t sclkl 60 - - ns SCLK Pulse Width High (SLAVE mode) t sclkh 60 - - ns SCLK rising to SDATA valid (SLAVE mode, Note 5) t dss - - 50 ns L/R edge to MSB valid (SLAVE mode) t lrdss - - 50 ns Falling SCLK to L/R edge delay (SLAVE mode, Note 5) t slr1 30 - - ns L/R edge to falling SCLK setup time (SLAVE mode, Note 5) t slr2 30 - - ns Falling SCLK to rising FSYNC delay (SLAVE mode, Note 5) t sfs1 30 - - ns Rising FSYNC to falling SCLK setup time (SLAVE mode, Note 5) t sfs2 30 - - ns DPD pulse width t pdw 2 x tclkw - - ns DPD rising to DCAL rising t pcr - - 50 ns DPD falling to DCAL falling (OWR = Output Word Rate) t pcf -4096- 1/OWR SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VL+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20 pF) Notes: 4. ICLKD rising or falling depends on DPD to L/R timing (see Figure 2). 5. SCLK is shown for CS5336, CS5338. SCLK is inverted for CS5339. 6. Specifies minimum output word rate (OWR) of 1 kHz. CS5336, CS5338, CS5339 3-42 DS23F1 |
类似零件编号 - CS5336-BP |
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类似说明 - CS5336-BP |
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