Adding slope compensation to the control loop, avoids

erratic operation of the PWM circuit, particularly at lower

duty cycles and higher frequencies, where there is not

enough ramp signal, and provides a more stable switch-

point.

The scheme that prevents that switching noise prematurely

triggers the PWM circuit consists of adding a positive volt-

age slope to the output of the Error Amplifier (COMP pin)

during an off-time cycle.

The circuit that implements this function for the syn-

Figure 6: Small RC filter provides the proper voltage ramp at the begin-

ning of each on-time cycle.

The ramp waveform is generated through a small RC filter

that provides the proper voltage ramp at the beginning of

Figure 6 form a voltage divider from the GATE(L) output,

superimposing a small artificial ramp on the output of the

error amplifier.

A similar approach can be used also for the non-syn-

this case, the slope compensation signal is generated direct-

ly from the GATE output, through the ac coupling capaci-

It is important that in both circuits, the series combination

negatively affect the slew rate on the GATE(L) and GATE

pins.

Figure 7: Slope compensation for the non-synchronous regulator section

Over-Current Protection

A loss-less hiccup mode current limit protection feature is

provided, requiring only the COMP capacitor to imple-

ment. The CS5132 provides overcurrent protection by sens-

ing the current through a “Droop” resistor, using an inter-

nal current sense comparator. The comparator compares

the voltage drop across the “Droop” resistor to an internal

reference voltage of 86mV (typical).

If the voltage drop across the “Droop” resistor exceeds this

threshold, the current sense comparator allows the fault

latch to be set. This causes the regulator to stop switching.

During this over current condition, the CS5132 stays off for

the time it takes the COMP pin capacitor to discharge to its

lower 0.25V threshold. As soon as the COMP pin reaches

0.25V, the Fault latch is reset (no overcurrent condition pre-

sent) and the COMP pin is charged with a 30µA current

Only at this point the regulator attempts to restart normal-

ly. The CS5132 will operate initially with a duty cycle

during the overcurrent condition (whether hiccup mode

was due to excessive current or hard short). This protection

scheme minimizes thermal stress to the regulator compo-

nents, input power supply, and PC board traces, as the over

current condition persists. Upon removal of the overload,

the fault latch is cleared, allowing normal operation to

resume.

Overvoltage Protection

Overvoltage protection (OVP) is provided as result of the

no additional external components. The control loop

responds to an overvoltage condition within 200ns, causing

the top MOSFET to shut off, disconnecting the regulator

from its input voltage. This results in a “crowbar” action to

clamp the output voltage and prevents damage to the load.

The regulator will remain in this state until the overvoltage

condition ceases or the input voltage is pulled low.

Additionally, a dedicated Overvoltage protection (OVP)

output pin (pin 21) is provided in the CS5132. The OVP sig-

nal will go high (overvoltage condition), if the output volt-

the voltage set by the particular DAC code. The OVP pin

can source up to 25mA of current that can be used to drive

an SCR to crowbar the power supply.

Power-Good Circuit

The Power-Good pin (pin 22) is an open-collector signal

consistent with TTL DC specifications. It is externally

pulled up, and is pulled low (below 0.3V) when the regula-

tor output voltage typically exceeds ± 8.5% of the nominal

output voltage. Maximum output voltage deviation before

Power-Good is pulled low is ± 12%.

Output Enable

On/off control of the regulator outputs can be implement-

ed by pulling the COMP pins low. It is required to pull the

COMP pins below the 1.06V PWM comparator offset volt-

age in order to disable switching on the GATE drivers.

Protection and Monitoring Features

15

13

GATE

COMP2

CS5132

Power Switch

To Synchronous FET

5

19

COMP1

GATE(L)

CS5132

Application Information: continued

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