sleep

wake

0.6V

2 2A

+

-

0.9V

V clamp

+

-

+

-

SS

logic

+

-

TSD

VDD_low

ss end

blanking

qn

qn

fpwm

Sync and

bootstrap

control

fpwm

LG

LG

5 2A

VDD_low

EN

FB

SW

SW

FPWM

COMP

PGOOD

SS

GND

SYNC

BOOT

VIN

VBIAS

VDD

VIN

SD

+

-

+

-

+

-

Clock / Sync

BG

BG

+

I Sense

PWM

Comp

BG

IREF

TSD

FPWM / Sleep

Peak Current

Control

Sleep

Reset

EA

PG

0.92BG

+

-

Corrective

Ramp

PWM Control

Logic

+

-

+

-

Sleep

Set

LDO

UVLO

on

Switchover

control

VREG

sleep

EP

frequency

foldback

FREQ

soft start

on

SD

ff

ff

1 2s/DIV

Vout

10 mV/Div

IL

500 mA/Div

ID

1A/Div

5V/Div

LM26001, LM26001-Q1

www.ti.com

SNVS430I – MAY 2006 – REVISED MARCH 2015

7 Detailed Description

7.1 Overview

The LM26001 is a current mode PWM buck regulator. At the beginning of each clock cycle, the internal high-side

switch turns on, allowing current to ramp up in the inductor. The inductor current is internally monitored during

each switching cycle. A control signal derived from the inductor current is compared to the voltage control signal

at the COMP pin, derived from the feedback voltage. When the inductor current reaches the threshold, the high-

side switch is turned off and inductor current ramps down. While the switch is off, inductor current is supplied

through the catch diode. This cycle repeats at the next clock cycle. In this way, duty cycle and output voltage are

controlled by regulating inductor current. Current mode control provides superior line and load regulation. Other

benefits include cycle by cycle current limiting and a simplified compensation scheme. Typical PWM waveforms

are shown in Figure 14.

Figure 14. PWM Waveforms 1-A Load, Vin = 12 V

7.2 Functional Block Diagram

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Product Folder Links: LM26001 LM26001-Q1