ISL29038

6

FN7851.1

January 23, 2015

Submit Document Feedback

ISL29038 Configuration and

Control

ISL29038 configuration and control is performed using the I2C

or SMBus. The ISL29038’s I2C interface slave address is

internally hard wired as 8’b1000100x, where x denotes the R/W

bit.

Every I2C transaction begins with the master asserting a start

condition (SDA falling while SCL remains high). The first

transmitted byte is initiated by the master and includes 7

address bits and a R/W bit. The slave is responsible for pulling

SDA low during the ACK time after every transmitted byte.

Figure 5 shows a sample one-byte read. The I2C bus master

always drives the SCL (clock) line, while either the master or the

slave can drive the SDA (data) line.

condition (SDA rising while SCL remains high). For more

specification documents.

Timing specifications are included in “I2C Electrical

Specifications” on page 4. The timing parameters are defined in

Figure 4.

byte read and write transfers using the random-read/write

protocol.

NOTE: That in most system implementations, the ISL29038 is connected

system performance.

START

W A

A

A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A

A6 A5 A4 A3 A2 A1 A0 W A

A

A

A D7 D6 D5 D4 D3D2 D1D0

13

5

7

13

57

1 2 3

4 5

6

9

2

4

6

STOP START

SDA DRIVEN BY MASTER

DEVICE ADDRESS

SDA DRIVEN BY ISL29038

DATA BYTE0

REGISTER ADDRESS

SLAVE

DEVICE ADDRESS

SDA DRIVEN BY MASTER

SDA DRIVEN BY MASTER

24

68 9

2

468 9

7

8

1

3

5

7 8

9

MASTER

(ISL29038)