TDA21231

Data Sheet

8

Table 11

Timing Characteristics

Parameter

Symbol

Values

Unit

Note / Test Condition

Min.

Typ.

Max.

PWM tri-state to SW rising

delay

t_pts

–

15

–

ns

PWM tri-state to SW falling

delay

t_pts2

–

15

–

SW Shutdown hold-Off time

from PWM low

t_tsshd

–

50

–

SW Shutdown hold-Off time

from PWM high

t_tssh

–

50

–

PWM to SW turn-off

propagation delay

t_pdlu

–

20

–

PWM to SW turn-on

propagation delay

t_pdll

–

10

–

DR_EN turn-off propagation

delay falling

t_pdl_DR_EN

–

20

–

DR_EN turn-on propagation

delay rising

t_pdh_DR_EN

–

20

–

UVLO-BOOT-on time

t_UVLOBOOTon

–

200

–

Pulse pattern issued to GL in

UVLO-BOOT

UVLO-BOOT-off time

t_UVLOBOOToff

–

200

–

PWM minimum pulse width

ton_min_PWM

–

25

–

When PWM change is

recognized, the output remains

in the new state for these

minimum times.

PWM minimum off time

toff_min_PWM

–

30

–

5

Theory of Operation

The TDA21231 incorporates a high performance gate driver, one high-side power MOSFET and one low-side

power MOSFET in a single PG-IQFN-31-2 package. The advantages of this arrangement are found in the

areas of increased performance, increased efficiency and lower overall package and layout inductance.This

module is ideal for use in Synchronous Buck Regulators.

The power MOSFETs are optimized for 5 V gate drive enabling excellent high load and light load efficiency. The

gate driver is a robust high-performance driver rated at the switching node for DC voltages ranging from -1 V to

+21 V. The power density for transmitted power of this approach is approximately 90 W within a 25 mm

5.1

Driver Characteristics

The gate driver of the TDA21231 has 2 voltage inputs, VCC and PVCC. VCC is the 5 V logic supply for the

driver. PVCC sets the driving voltage for the high side and low side MOSFETs. The reference for the gate driver

control circuit (VCC) is AGND. To decouple the sensitive control circuitry (logic supply) from a noisy

environment a ceramic capacitor must be placed between VCC and AGND close to the pins. PVCC needs also

to be decoupled using a ceramic capacitor (MLCC) between PVCC and PGND in close proximity to the pins.

PGND serves as reference for the power circuitry including the driver output stage.