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ISL22323WFV14Z 数据表(PDF) 3 Page - Intersil Corporation |
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ISL22323WFV14Z 数据表(HTML) 3 Page - Intersil Corporation |
3 / 19 page 3 FN6422.2 August 17, 2015 Pin Descriptions TSSOP PIN QFN PIN SYMBOL DESCRIPTION 1 11 RH0 “High” terminal of DCP0 2 12 RL0 “Low” terminal of DCP0 3 13 RW0 “Wiper” terminal of DCP0 4 14 RH1 “High” terminal of DCP1 5 15 RL1 “Low” terminal of DCP1 6 16 RW1 “Wiper” terminal of DCP1 7 1 A2 Device address input for the I2C interface 8 4 V- Negative power supply pin 9 5 SDA Open drain Serial data I/O for the I2C interface 10 6 SCL I2C interface clock input 11 7 GND Device ground pin 12 8 A1 Device address input for the I2C interface 13 9 A0 Device address input for the I2C interface 14 10 VCC Positive power supply pin 2, 3 NC No connection EPAD* Exposed Die Pad internally connected to V- NOTE: *PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf ISL22323 |
类似零件编号 - ISL22323WFV14Z |
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类似说明 - ISL22323WFV14Z |
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