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ISL5761EVAL1 数据表(PDF) 3 Page - Intersil Corporation

部件名 ISL5761EVAL1
功能描述  10-bit, 3.3V, 130/210MSPS, High Speed D/A Converter
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

ISL5761EVAL1 数据表(HTML) 3 Page - Intersil Corporation

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Pin Descriptions
PIN NO.
PIN NAME
DESCRIPTION
1-10
D9 (MSB) Through
D0 (LSB)
Digital Data Bit 9, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
15
SLEEP
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin
has internal 20
A active pulldown current.
16
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference.
17
REFIO
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.
F cap to ground when internal reference is enabled.
18
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current
= 32 x VFSADJ/RSET.
19, 25
NC
No Connect. These should be grounded, but can be left disconnected.
21
IOUTB
The complementary current output of the device. Full scale output current is achieved when all input bits are
set to binary 0.
22
IOUTA
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23
COMP
Connect 0.1
F capacitor to ACOM.
24
AVDD
Analog Supply (+3.0V to +3.6V).
20
ACOM
Connect to Analog Ground.
26, 11-14
DCOM
Connect to Digital Ground.
27
DVDD
Digital Supply (+3.0V to +3.6V).
28
CLK
Clock Input.
ISL5761


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