Phase

Detector

Loop

Filter

Variable

Delay

÷2

÷2

14bit

2.4Gsps

DAC

Input

Registers

Demux

and

Format

DA_P[13:0]

DA_N[13:0]

DB_P[13:0]

DB_N[13:0]

DLYCLK_P

DLYCLK_N

DTCLK_P

DTCLK_N

Bandgap

Ref

REFIO_IN

REFIO

RBIASOUT

RBIASIN

CSBIAS

CSBIAS_IN

IOUT_P

IOUT_N

INV_CLK

ModeControls

RESTART

LOCK

SLEEP

Phase

Detector

Loop

Filter

Variable

Delay

÷2

÷2

14bit

2.4Gsps

DAC

Input

Registers

Demux

and

Format

DA_P[13:0]

DA_N[13:0]

DB_P[13:0]

DB_N[13:0]

DLYCLK_P

DLYCLK_N

DTCLK_P

DTCLK_N

Bandgap

Ref

REFIO_IN

REFIO

RBIASOUT

RBIASIN

CSBIAS

CSBIAS_IN

IOUT_P

IOUT_N

INV_CLK

ModeControls

RESTART

SLEEP

Product

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DAC5670-SP

SGLS386F – JANUARY 2009 – REVISED OCTOBER 2014

DAC5670-SP 14-Bit 2.4-GSPS Digital-to-Analog Converter (DAC)

1 Features

3 Description

The DAC5670 is a 14-bit 2.4-GSPS DAC with dual

1

•

14-Bit Resolution

demultiplexed differential input ports. The DAC5670

•

2.4-GSPS Max Update Rate DAC

is clocked at the DAC sample rate and the two input

•

Dual Differential Input Ports

ports run at a maximum of 1.2 GSPS. An additional

reference bit input sequence is used to adjust the

–

Even/Odd Demultiplexed Data

output clock delay to the data source, optimizing the

–

Maximum 1.2 GSPS Each Port, 2.4 GSPS

internal data latching clock relative to this reference

Total

bit with a delay lock loop (DLL). Alternatively, the DLL

–

Dual 14-Bit Inputs + 1 Reference Bit

may be bypassed and the timing interface managed

by controlling DATA setup and hold timing to

–

DDR Output Clock

DLYCLK.

–

DLL Optimized Clock Timing Synchronized to

The DAC5670 can also accept data up to 1.2 GSPS

Reference Bit

using only the A input port. In the single port modes,

–

LVDS and HyperTransport™ Voltage Level

options include: repeating the input sample (A_ONLY

Compatible

mode), 2× interpolation by zero stuff (A_ONLY_ZS

–

Internal 100-

Ω Terminations for Data and

mode), or 2× interpolation by repeating and inverting

Reference Bit Inputs

the input sample (A_ONLY_INV). These modes are

used to double the input sample rate up to 2.4 GSPS.

•

Selectable 2× Interpolation With Fs / 2 Mixing

•

Differential Scalable Current Outputs: 5 to 30 mA

The DAC5670 operates with a single 3- to 3.6-V

supply voltage. Power dissipation is 2 W at maximum

•

On-Chip 1.2-V Reference

operating

conditions.

The

DAC5670

provides

a

•

3.3-V Analog Supply Operation

nominal full-scale differential current-output of 20 mA,

•

Power Dissipation: 2 W

supporting

both

single-ended

and

differential

applications.

An

on-chip

1.2-V

temperature-

•

192-Ball CBGA (GEM) Package

compensated

bandgap

reference

and

control

•

QML-V Qualified, SMD 5962-07247

amplifier allows the user to adjust the full-scale output

•

Military Temperature Range (–55°C to 125°C

current from the nominal 20 mA to as low as 5 mA or

as high as 30 mA.

2 Applications

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

Test and Measurement: Arbitrary Waveform

DAC5670-SP

CBGA (192)

19.00 mm × 19.00 mm

Generator

•

Communications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Engineering evaluation (/EM) samples are

available

Simplified Schematic

(1)

These units are intended for engineering evaluation only.

They are processed to a non-compliant flow (that is, no burn-

in, and so forth) and are tested to a temperature rating of

25°C only. These units are not suitable for qualification,

production, radiation testing, or flight use. Parts are not

warranted for performance over the full MIL specified

temperature range of –55°C to 125°C or operating life.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.