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TS3DV642 数据表(PDF) 5 Page - Texas Instruments |
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TS3DV642 数据表(HTML) 5 Page - Texas Instruments |
5 / 30 page TS3DV642 www.ti.com SCDS343C – MAY 2013 – REVISED NOVEMBER 2014 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage range –0.5 5.5 V VI/O Analog voltage range(2)(3)(4) All I/O –0.5 5.5 V VIN Digital input voltage range(2)(3) SEL1, SEL2, EN –0.5 5.5 V II/OK Analog port diode current VI/O < 0 –50 mA IIK Digital input clamp current VIN < 0 –50 mA II/O On-state switch current(5) –128 128 mA (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground, unless otherwise specified. (3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (4) VI and VO are used to denote specific conditions for VI/O. (5) II and IO are used to denote specific conditions for II/O. 7.2 Handling Ratings MIN MAX UNIT Tstg Storage temperature range –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –2000 2000 pins(1) V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification –1000 1000 JESD22-C101, all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage 2.6 4.5 V VI/O Input/Output voltage 0 5.5 V TA Operating free-air temperature –40 85 °C (1) All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 7.4 Thermal Information TS3DV642 THERMAL METRIC(1) QFN UNIT 42 PINS RθJA Junction-to-ambient thermal resistance 31.5 RθJC(top) Junction-to-case (top) thermal resistance 16.2 RθJB Junction-to-board thermal resistance 5.5 °C/W ψJT Junction-to-top characterization parameter 0.2 ψJB Junction-to-board characterization parameter 5.4 RθJC(bot) Junction-to-case (bottom) thermal resistance 2.0 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TS3DV642 |
类似零件编号 - TS3DV642_15 |
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类似说明 - TS3DV642_15 |
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