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TSI381 数据表(PDF) 1 Page - Integrated Device Technology |
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TSI381 数据表(HTML) 1 Page - Integrated Device Technology |
1 / 2 page 1 of 2 August 14, 2009 2008 Integrated Device Technology, Inc. IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. ® Features General • PCI Express to PCI bridge • Transparent, Non-transparent, and Opaque modes • Efficient queuing and buffering for low latency and high throughput • Compliant with the following specifications: – PCI Express Base 1.1 – PCI Express PCI/PCI-X Bridge 1.0 – PCI-to-PCI Bridge Architecture 1.2 – PCI Local Bus 3.0 – PCI Bus Power Management Interface 1.2 PCI Express • x1 lane PCIe Interface • Advanced error reporting capability • End-to-end CRC check and generation • Up to four outstanding memory reads • ASPM L0 link state power management • Legacy interrupt signaling and MSI interrupts • Hot Plug support PCI • 32/64-bit addressing and 32-bit data • Operates at 25, 33, 50, and 66 MHz • Up to eight outstanding memory reads • 3.3V PCI I/Os, 5V tolerant • Four external PCI masters supported through internal arbiter • MSI generation and handling using interrupt and GPIO signals Other Features • Masquerade mode • JTAG IEEE 1149.1, 1149.6 to allow testing of the PCIe Interface • Four GPIO pins and four interrupt pins that can generate MSIs • D0, D3 hot, D3 cold power management state support • 1.2V core power supply • No power sequencing constraints • Packaging: – 13x13 mm, 144-pin PBGA (10x10 mm option is available; part number Tsi382) – Pinout and footprint compatible with PLX PEX 8111/8112 – Industrial temperature operating range – RoHS-compliant package available Device Overview The IDT Tsi381 is a high-performance bus bridge that connects the PCI Express protocol to the PCI bus standard. The Tsi381’s PCIe Inter- face supports a x1 lane PCIe configuration, which enables the bridge to offer exceptional throughput performance of up to 2.5 Gbps per transmit and receive direction. The device’s PCI Interface can operate up to 66 MHz. This interface offers designers extensive flexibility by supporting three types of addressing modes: transparent, opaque, and non-transparent. Figure 1 Block Diagram Simplest, Low-Risk Design The Tsi381 simplifies board design by using only two power supplies with no power sequencing constraints. Its package is designed to simplify board layout for high reliability and signal integrity. A compre- hensive suite of design support resources are also available to aid designers. Pin compatibility with the PLX PEX8111 and PEX8112 make it easy for designers to migrate current designs to the Tsi381, and thereby bring them to market quickly and with low risk. Interrupt Handling Clocking/ Reset EEPROM Controller Power Mgmt JTAG PCI Interface PCIe Interface (x1) 80E2000_BK001_03 (Tsi381) Posted Writer Buffer Posted Queue Mux Logic Non- Posted Buffer Non- Posted Queue Posted Writer Buffer Posted Queue Mux Logic Non- Posted Buffer Non- Posted Queue Downstream Downstream Upstream Upstream PCI Arbiter Config Registers GPIO Error Handling Tsi381™ PCIe® to PCI Bridge Product Brief |
类似零件编号 - TSI381 |
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类似说明 - TSI381 |
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