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74ALVC125 数据表(PDF) 7 Page - NXP Semiconductors |
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74ALVC125 数据表(HTML) 7 Page - NXP Semiconductors |
7 / 13 page 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 7 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 7. Enable and disable times mna362 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nOE input VI VOL VOH VCC VM GND GND tPZL tPZH VM VM Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Test circuitry for switching times VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 k Ω open 2 × V CC GND 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × V CC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6 V GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6 V GND |
类似零件编号 - 74ALVC125_15 |
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类似说明 - 74ALVC125_15 |
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