LF3347 datasheet(3/10 Pages) LODEV

部件名	LF3347

功能描述	High-Speed Image Filter with Coefficient RAM

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制造商	LODEV [LOGIC Devices Incorporated]

网页	http://www.logicdevices.com

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DEVICES INCORPORATED

Video Imaging Products

LF3347

High-Speed Image Filter with Coefficient RAM

08/16/2000–LDS.3347-G

3

OCEN — Output Clock Enable

When OCEN is LOW, the output

register is enabled for data loading.

When OCEN is HIGH, output register

loading is disabled and the register’s

contents will not change.

ACC — Accumulator Control

The ACC input determines whether

internal accumulation is performed. If

ACC is LOW, no accumulation is

performed, the prior accumulated sum

is cleared, and the current sum of

products is output. When ACC is

HIGH, the emerging product is added

to the sum of the previous products.

LD — Load Control

LD enables the loading of data into the

coefficient banks and control registers

(control registers are the round and limit

registers). When LD is LOW, data on

CC11-0 is latched into the device on the

rising edge of CCCLK. When LD is

HIGH, data cannot be loaded into the

coefficient banks and control registers.

When enabling the input circuitry for

data loading, the LF3347 requires a

HIGH to LOW transition of LD in order

to function properly. Therefore, LD

needs to be set HIGH immediately after

power up to ensure proper operation of

the input circuitry.

It takes five CCCLK clock cycles to load

one coefficient set into the four coefficient

banks or to load one control register.

When the input circuitry is enabled (LD

goes LOW), the first value loaded into the

device on CC11-0 is an address which

determines what will be loaded (see

Table 2). The next four values loaded on

CC11-0 is the data to be loaded into the

coefficient banks or control register (see

Tables 3-5). After the last data value is

loaded, another coefficient bank address

or control register may be loaded by

feeding another address into CC11-0.

When all desired coefficient banks and

control registers are loaded, the input

circuitrymustbedisabledbysettingLDHIGH.

SELRND3-0 — Round Select

SELRND3-0 allows the user to select

which rounding register will be used

in the rounding circuit to round/offset

the data.

SHIFT4-0 — Shift

SHIFT4-0 determines which 16-bits of

the 32-bits from the accumulator are

passed to the output (see Table 1).

SELLMT3-0 — Limit Select

SELLMT3-0 allows the user to control

which limiting register will be used in

the limiting circuit to set the upper

and lower limits on the data.

LMTEN — Limit Enable

When LMTEN is LOW, limiting is

enabled and the selected limit register

is used to determine the valid range of

output values for the overall filter.

When HIGH, limiting is disabled.

FIGURE 2. ROUNDING, SELECTING,

LIMITING CIRCUITRY

RND

SELECT

LIMIT

32

16

LMTEN

32

SHIFT4-0

ULMT15-0

LLMT15-0

RND31-0

16

32

Register

Load Address

Bits

Register Description

A7-0

SELRND3-0 SELLMT3-0

CS0

000H

11-0

Coefficient Set 0

00H

CS1

001H

11-0

Coefficient Set 1

01H

···

·

···

·

···

·

CS255

0FFH

11-0

Coefficient Set 255

FFH

RND0

800H

31-0

Rounding Register 0

0 0 0 0

RND1

801H

31-0

Rounding Register 1

0 0 0 1

···

·

···

·

···

·

RND15

80FH

31-0

Rounding Register 15

1 1 1 1

LMT0

C00H

31-16/15-0

Upper / Lower Limit Register 0

0 0 0 0

LMT1

C01H

31-16/15-0

Upper / Lower Limit Register 0

0 0 0 1

···

·

···

·

···

·

LMT15

C0FH

31-16/15-0

Upper / Lower Limit Register 15

1 1 1 1

TABLE 2.

REGISTER FORMATS

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