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PD16326A 数据表(PDF) 7 Page - Renesas Technology Corp |
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PD16326A 数据表(HTML) 7 Page - Renesas Technology Corp |
7 / 14 page µPD16326A 5 SWITCHING CHARACTERISTICS (TA = 25 ˚C, VDD1 = 5.0 V, VDD2 = 130 V, VSS = 0 V, logic CL = 15 pF, driver CL = 50 pF, driver RL = 220 k Ω, tr = tf = 10 ns) Item Symbol Condition MIN. TYP. MAX. Unit Transmission delay time tPHL1 CLK ↓→ A/B 110 ns tPLH1 110 ns tPHL2 BLK ↓→ O1 to O32 300 ns tPLH2 300 ns Fall time tTHL O1 to O32 600 ns Rise time tTLH O1 to O32 500 ns Maximum clock frequency fmax With cascading, Duty = 50 % 8.0 MHz Input capacitance CI 15 pF TIMING REQUIREMENTS (TA = – 40 to +85 ˚C, VDD1 = 4.5 to 5.5 V, VSS = 0 V, tr = tf = 10 ns) Item Symbol Condition MIN. TYP. MAX. Unit Clock pulse width PWCLK 40 ns Strobe pulse width PWSTB 80 ns Blank pulse width PWBLK 1 500 ns Data setup time tsetup 15 ns Data hold time thold 30 ns Clock-strobe time tCLK-STB CLK ↓→ STB ↑ 45 ns Strobe-clock time tSTB-CLK STB ↓→ CLK ↓ 45 ns Strobe-blank time tSTB-BLK STB ↑→ BLK ↓ 80 ns |
类似零件编号 - PD16326A_15 |
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类似说明 - PD16326A_15 |
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