PD17P719_15 datasheet(4/42 Pages) RENESAS

部件名	PD17P719

功能描述	MOS INTEGRATED CIRCUIT

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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µPD17P719

Item

(1/2)

Product

µPD17717

µPD17718

µPD17719

µPD17P719

16384

× 16 bits

(one-time PROM)

16384

× 16 bits

(masked ROM)

12288

× 16 bits

(masked ROM)

1120

× 4 bits

1.78

µs (with fX = 4.5-MHz crystal)

• I/O ports

: 46

• Input ports

: 12

• Output ports : 4

• Address stack : 15 levels

• Interrupt stack : 4 levels

• DBF stack

: 4 levels (operated by software)

• External : 6 (CE rising edge and INT0 to INT4)

• Internal : 6 (timers 0 to 3, serial interfaces 0 and 1)

5 channels

• Basic timer (clock: 10, 20, 50, 100 Hz)

: 1 channel

• 8-bit timer with gate counter (clock: 1 k, 2 k, 10 k, 100 kHz)

: 1 channel

• 8-bit timer (clock: 1 k, 2 k, 10 k, 100 kHz)

: 2 channels

• 8-bit timer, also used for PWM (clock: 440 Hz, 4.4 kHz)

: 1 channel

8 bits

× 6 channels (Hardware or software mode can be selected.)

3 channels (8-bit or 9-bit resolution, selected by software.)

Output frequency : 4.4 kHz, 440 Hz (8-bit PWM)

2.2 kHz, 220 Hz (9-bit PWM)

2 systems (4 channels)

• Selectable for 3-wire serial I/O method, SBI method, 2-wire serial I/O method, or I2C bus

methodNote.

• Selectable for 3-wire serial I/O method or UART method.

• Direct frequency division system (VCOL pin (MF mode)

: 0.5 to 3 MHz)

• Pulse swallow system

(VCOL pin (HF mode)

: 10 to 40 MHz)

(VCOH pin (VHF mode) : 60 to 130 MHz)

Can be set to one of 13 frequencies

(1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, or 50 kHz).

2 error output pins (EO0 and EO1)

Unlock detection is enabled by software.

• Intermediate frequency (IF) measurement

P1C0/FMIFC pin : 10 to 11 MHz in FMIF mode

0.4 to 0.5 MHz in AMIF mode

P1C1/AMIFC pin : 0.4 to 0.5 MHz in AMIF mode

• External gate width measurement

P2A1/FCG1 and P2A0/FCG0 pins

Program memory (ROM)

General-purpose data

memory (RAM)

Instruction execution time

General-purpose ports

Stack level

Interrupt

Timers

A/D converter

D/A converter

(PWM)

Serial interface

PLL

Intermediate frequency

counter

1776

× 4 bits

Frequency

division

system

Reference

frequency

Charge pump

Phase comparator

FUNCTION OVERVIEW

Note

When ordering a mask, please consult our sales office if the I2C bus method is used (or when the serial

interface is accomplished by the program not by the peripheral hardware).

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