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ADV7324 数据表(PDF) 11 Page - Analog Devices |
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ADV7324 数据表(HTML) 11 Page - Analog Devices |
11 / 92 page ADV7324 Rev. 0 | Page 11 of 92 t9 t11 t10 t12 t11 t12 t13 t14 CLKIN_B* *CLKIN_B USED IN THIS PS ONLY MODE Y9–Y0 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME CONTROL OUTPUTS Y1 Cr0 Y0 Cb0 XY 00 00 3FF Figure 8. PS Only 4:2:2 10-Bit Interleaved at 27 MHz EAV/SAV Input Mode (Input Mode 100) t9 t11 t10 t12 t14 t13 CLKIN_A Y9–Y0 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME CONTROL OUTPUTS NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01, BIT 1 3FF 00 00 XY Cb0 Y0 Cr0 Y1 Figure 9. PS Only 4:2:2 10-Bit Interleaved at 54 MHz EAV/SAV Input Mode (Input Mode 111) t9 t11 t10 t12 Y0 Y1 Y2 Y3 Y4 Y5 t9 t10 t11 t12 HD INPUT SD INPUT S9–S0 CONTROL INPUTS CLKIN_A CLKIN_B Y9–Y0 CONTROL INPUTS C9–C0 P_HSYNC, P_VSYNC, P_BLANK Y2 Cb1 Y1 Cr0 Y0 Cb0 S_HSYNC, S_VSYNC, S_BLANK Cr4 Cb4 Cr2 Cb2 Cr0 Cb0 Figure 10. HD 4:2:2 and SD 10-Bit Simultaneous Input Mode (Input Mode 101: SD Oversampled) (Input Mode 110: HD Oversampled) |
类似零件编号 - ADV7324_15 |
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类似说明 - ADV7324_15 |
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