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ADV7183A 数据表(PDF) 11 Page - Analog Devices |
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ADV7183A 数据表(HTML) 11 Page - Analog Devices |
11 / 104 page ADV7183A Rev. B | Page 11 of 104 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 2 HS 3 DGND 4 DVDDIO 7 P9 6 P10 5 P11 1 VS 8 P8 9 DGND 10 DVDD 12 SFL 13 NC 14 DGND 15 DVDDIO 16 NC 17 NC 18 NC 19 P7 20 P6 11 NC 59 58 57 54 55 56 60 53 52 AIN11 AIN4 AIN10 CAP C1 CAP C2 AGND AIN5 AGND CML 51 REFOUT 49 CAP Y2 48 CAP Y1 47 AGND 46 AIN3 45 AIN9 44 AIN2 43 AIN8 42 AIN1 41 AIN7 50 AVDD NC = NO CONNECT 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PIN 1 ADV7183A TOP VIEW (Not to Scale) Figure 5. 80-Lead LQFP Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Type Function 3, 9, 14, 31, 71 DGND G Digital Ground. 39, 40, 47, 53, 56 AGND G Analog Ground. 4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V). 10, 30, 72 DVDD P Digital Core Supply Voltage (1.8 V). 50 AVDD P Analog Supply Voltage (3.3 V). 38 PVDD P PLL Supply Voltage (1.8 V). 42, 44, 46, 58, 60, 62, 41, 43, 45, 57, 59, 61 AIN1–AIN12 I Analog Video Input Channels. 11, 13, 16–18, 25, 34, 35, 63, 65, 69, 70, 77, 78 NC No Connect Pins. 33, 32, 24, 23, 22, 21, 20, 19, 8, 7, 6, 5, 76, 75, 74, 73 P0–P15 O Video Pixel Output Port. 2 HS O Horizontal Synchronization Output Signal. 1 VS O Vertical Synchronization Output Signal. 80 FIELD O Field Synchronization Output Signal. 67 SDA I/O I2C Port Serial Data Input/Output Pin. 68 SCLK I I2C Port Serial Clock Input (Max Clock Rate of 400 kHz). 66 ALSB I This pin selects the I2C address for the ADV7183A. ALSB set to Logic 0 sets the address for a write as 0x40; for ALSB set to logic high, the address selected is 0x42. 64 RESET I System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7183A circuitry. |
类似零件编号 - ADV7183A_15 |
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类似说明 - ADV7183A_15 |
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