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ADV473 数据表(PDF) 11 Page - Analog Devices |
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ADV473 数据表(HTML) 11 Page - Analog Devices |
11 / 12 page ADV473 –11– REV. A PC BOARD LAYOUT CONSIDERATIONS The layout should be optimized for lowest noise on the ADV473 power and ground lines by shielding the digital inputs and pro- viding good decoupling. The lead length between groups of VAA and GND pins should be minimized so as to minimize inductive ringing. Ground Planes The ground plane should encompass all ADV473 ground pins, current/voltage reference circuitry, power supply bypass circuitry for the ADV473, the analog output traces, and all the digital sig- nal traces leading up to the ADV473. Power Planes The ADV473 and any associated analog circuitry should have its own power plane, referred to as the analog power plane. This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figures 7 and 8. This bead should be located within three inches of the ADV473. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV473 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable opera- tion, to reduce the lead inductance. Best performance is ob- tained with a 0.1 µF ceramic capacitor decoupling each of the two groups of VAA pins to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV473 contains circuitry to reject power supply noise, this rejection decreases with fre- quency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and should consider using a three-terminal voltage regula- tor for supplying power to the analog power plane. Digital Signal Interconnect The digital inputs to the ADV473 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV473 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not to the analog power plane. ANALOG POWER PLANE IOR IOG IOB V AA ADV473 V REFIN 75 Ω 75 Ω V REFOUT CO-AXIAL CABLE (75 Ω) GND BNC CONNECTORS 75 Ω 75 Ω 75 Ω MONITOR (CRT) 0.1 µF 10 µF POWER SUPPLY DECOUPLING (0.1 µF CAPACITOR FOR EACH V REF GROUP ) 0.1 µF L1 (FERRITE BEAD) COMP COMP +5V (V AA ) 0.1 µF +5V (V AA ) +5V (V CC ) +5V (V AA ) 0.1 µF 1k Ω (1% METAL) AD589 (1.2 V REF ) COMPONENT DESCRIPTION VENDOR PART NUMBER C1 – C5 0.1 µF CERAMIC CAPACITOR ERIE RPE112Z5U104M50V C6 10 µF TANTALUM CAPACITOR MALLORY CSR13G106KM L1 FERRITE BEAD FAIR-RITE 2743001111 R1, R2, R3 75 Ω 1% METAL FILM RESISTOR R4 1k Ω 5% RESISTOR R SET 1% METAL FILM RESISTOR Z1 1.23V VOLTAGE REFERENCE AD589JN R SET 140 Ω R SET 0.1 µF 75 Ω Figure 7. Typical Connection Diagram (External Voltage Reference) |
类似零件编号 - ADV473_15 |
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类似说明 - ADV473_15 |
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