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ISL5961IA 数据表(PDF) 3 Page - Intersil Corporation |
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ISL5961IA 数据表(HTML) 3 Page - Intersil Corporation |
3 / 13 page 3 Pin Descriptions PIN NO. PIN NAME DESCRIPTION 1-14 D13 (MSB) Through D0 (LSB) Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). 15 SLEEP Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20 µA active pulldown current. 16 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. 17 REFIO Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0. 1µF cap to ground when internal reference is enabled. 18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. 19, 25 NC No Connect. These should be grounded, but can be left disconnected. 21 IOUTB The complementary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. 22 IOUTA Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. 23 COMP Connect 0.1 µF capacitor to ACOM. 24 AVDD Analog Supply (+2.7V to +3.6V). 20 ACOM Connect to Analog Ground. 26 DCOM Connect to Digital Ground. 27 DVDD Digital Supply (+2.7V to +3.6V). 28 CLK Clock Input. ISL5961 |
类似零件编号 - ISL5961IA |
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类似说明 - ISL5961IA |
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