ADF4001_15 datasheet(10/17 Pages) AD

部件名	ADF4001

功能描述	200 MHz Clock Generator PLL

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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10 / 17 page

REV.

ADF4001

–10–

Table V. Function Latch Map

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

C2 (1) C1 (0)

F1

PD1

M1

M2

M3

F3

CPI1

CPI2

CPI5

CPI6

TC4

PD2

F2

CONTROL

BITS

MUXOUT

CONTROL

CURRENT

SETTING

1

TIMER COUNTER

CONTROL

CPI3

CPI4

DB21

CURRENT

SETTING

2

TC3

TC2

TC1

DB22

DB23

F4

F5

RESERVED

CE PIN

PD2

PD1

MODE

0

XXASYNCHRONOUS POWER-DOWN

1X

0NORMAL OPERATION

101ASYNCHRONOUS POWER-DOWN

111SYNCHRONOUS POWER-DOWN

CPI6

CPI5

CP14

ICP (mA)

CPI3

CPI2

CPI1

2.7k

4.7k

10k

000

1.088

0.625

0.294

001

2.176

1.25

0.588

010

3.264

1.875

0.882

011

4.352

2.5

1.176

100

5.44

3.125

1.47

101

6.528

3.75

1.764

110

7.616

4.375

2.058

111

8.704

5.0

2.352

TIMEOUT

TC4

TC3

TC2

TC1

(PFD CYCLES)

00003

00017

0010

11

0011

15

0100

19

0101

23

0110

27

0111

31

1000

35

1001

39

1010

43

1011

47

1100

51

1101

55

1110

59

1111

63

F4

F5

FASTLOCK MODE

0X

FASTLOCK DISABLED

10

FASTLOCK MODE 1

11

FASTLOCK MODE 2

F3

CHARGE PUMP OUTPUT

0NORMAL

1THREE-STATE

M3

M2

M1

OUTPUT

000

THREE-STATE OUTPUT

001DIGITAL LOCK DETECT

010

N DIVIDER OUTPUT

011

AVDD

100

R DIVIDER OUTPUT

101

N-CHANNEL OPEN-DRAIN

LOCK DETECT

110SERIAL DATA OUTPUT

111

DGND

PHASE DETECTOR

F2

POLARITY

0NEGATIVE

1POSITIVE

COUNTER

F1

OPERATION

0

NORMAL

1

R, N COUNTER

HELD IN RESET

X = DON’T CARE

X

B

类似零件编号 - ADF4001_15

制造商	部件名	数据表	功能描述
Analog Devices	ADF4001BCP	190Kb / 16P	200 MHz Clock Generator PLL REV. 0
	ADF4001BCP	929Kb / 28P	50 MHz to 1000 MHz Quadrature Demodulator REV. A
	ADF4001BCPZ	860Kb / 17P	200 MHz Clock Generator PLL REV. B
	ADF4001BCPZ-RL	860Kb / 17P	200 MHz Clock Generator PLL REV. B
	ADF4001BCPZ-RL7	860Kb / 17P	200 MHz Clock Generator PLL REV. B

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类似说明 - ADF4001_15

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