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AD8184 数据表(PDF) 3 Page - Analog Devices |
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AD8184 数据表(HTML) 3 Page - Analog Devices |
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3 / 12 page  ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V Internal Power Dissipation 2 AD8184 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts AD8184 14-Lead Small Outline (R) . . . . . . . . . . 1.0 Watts Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V S Output Short Circuit Duration . . Observe Power Derating Curves Storage Temperature Range N & R Package . . . . . . . . . . . . . . . . . . . . . –65 °C to +125°C Lead Temperature Range (Soldering 10 sec) . . . . . . . +300 °C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Specification is for device in free air: 14-pin plastic package: θ JA = 75°C/Watt 14-pin SOIC package: θ JA = 120°C/Watt, where PD = (TJ –TA)/θJA. ORDERING GUIDE Temperature Package Package Model Range Description Option AD8184AN –40 °C to +85°C 14-Lead Plastic DIP N-14 AD8184AR –40 °C to +85°C 14-Lead Narrow SOIC R-14 AD8184AR-REEL –40 °C to +85°C Reel 14-Lead SOIC R-14 AD8184-EB Evaluation Board For AD8184R MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8184 is limited by the associated rise in junction temperature. The maxi- mum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150 °C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175 °C for an extended period can result in device failure. NOTES 1ENABLE pin is grounded. IN0 and IN2 = +1 V dc, IN1 and IN3 = –1 V dc. A0 is driven with a 0 V to +5 V pulse, A1 is grounded. Measure transition time from 50% of the A0 input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (–1 V), or vice versa. All inputs are measured in a similar manner using A0 and A1 to select the channels. 2ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). The state of the A0 and A1 pins determines which input is activated (refer to Table I). Set IN0 and IN2 = +1 V dc, IN1 and IN3 = –1 V dc, and measure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 4, ∆t OFF is the disable time, ∆tON is the enable time. 3All inputs are grounded. A0 input is driven with 0 V to +5 V pulse, A1 is grounded. The output is monitored. Speeding the edges of the A0 pulse increases the glitch magnitude due to coupling via the ground plane. Removing the A0 and A1 terminations will lower the glitch, as does increasing RL. 4Decreasing R L slightly lowers the bandwidth. Increasing CL significantly lowers the bandwidth (see Figure 18). 5A resistor (R S) placed in series with the multiplexer inputs serves to optimize 0.1 dB flatness, but is not required (see Figure 19.) 6Select an input that is not being driven (i.e., A0 and A1 are logic 0, IN0 is selected); drive all other inputs with V IN = 0.707 V rms and monitor the output at ƒ = 5 and 30 MHz. RL = 2 kΩ (see Figure 12). 7Multiplexer is disabled (i.e., ENABLE = logic 1) and all inputs are driven simultaneously with V IN = 0.446 V rms. Output is monitored at ƒ = 5 and 30 MHz. RL = 30 Ω to simu- late RON of one enabled multiplexer within a system (see Figure 13). In this mode the output impedance is very high (typ 10 MΩ), and the signal couples across the package; the load impedance determines the crosstalk. 8Voltage gain decreases for lower values of R L. The resistive divider formed by the multiplexers enables output resistance (28 Ω) and RL causes a gain that increases as RL- decreases (i.e., the voltage gain is approximately 0.97 V/V [3% gain error] for RL = 1 kΩ). 9Larger values of R L provide wider output voltage swings, as well as better gain accuracy. See Note 8. Specifications subject to change without notice. AD8184 –3– REV. 0 While the AD8184 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction tempera- ture (+150 °C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 2. AMBIENT TEMPERATURE – °C 2.5 2.0 0.5 –50 90 –40 –30 –20 –10 0 10 20 30 40 50 60 80 1.5 1.0 70 14-PIN SOIC 14-PIN DIP PACKAGE TJ = +150°C Figure 2. Maximum Power Dissipation vs. Temperature WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8184 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. |
类似零件编号 - AD8184_15 |
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类似说明 - AD8184_15 |
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