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AD8133 数据表(PDF) 5 Page - Analog Devices |
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AD8133 数据表(HTML) 5 Page - Analog Devices |
5 / 16 page AD8133 Rev. 0 | Page 5 of 16 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage 12 V All VOCM ±VS Power Dissipation See Figure 3 Input Common-Mode Voltage ±VS Storage Temperature −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature Range (Soldering 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat- ing only and functional operation of the device at these or any other conditions above those indicated in the operational sec- tion of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, i.e., θJA is specified for the device soldered in a circuit board in still air. Table 4. Thermal Resistance with the Underside Pad Connected to the Plane Package Type/PCB Type θJA Unit 24-Lead LFCSP/4-Layer 70 °C/W Maximum Power Dissipation The maximum safe power dissipation in the AD8133 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the para- metric performance of the AD8133. Exceeding a junction tem- perature of 175°C for an extended period of time can result in changes in the silicon devices potentially causing failure. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The load current consists of differential and common-mode currents flowing to the loads, as well as currents flowing through the internal differential and common- mode feedback loops. The internal resistor tap used in the common-mode feedback loop places a 4 kΩ differential load on the output. RMS output voltages should be considered when dealing with ac signals. Airflow reduces θJA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a copper plane in order to achieve the specified θJA. Figure 3 shows the maximum safe power dissipation in the package versus ambient temperature for the 24-lead LFCSP (70°C/W) package on a JEDEC standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a PCB plane. θJA values are approximations. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –40 –20 0 20 40 60 80 AMBIENT TEMPERATURE ( °C) LFCSP Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprie- tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. |
类似零件编号 - AD8133_15 |
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类似说明 - AD8133_15 |
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