CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.

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1

SEMICONDUCT OR

CD54AC299/3A

CD54ACT299/3A

8-Input Universal Shift/Storage Registers

with Common Parallel I/O Pins

2. When both S0 and S1 are HIGH, I/O terminals are in the

high-impedance state but being input ports, ready for par-

allel data to be loaded into eight registers with one clock

transition regardless of the status of OE1 and OE2.

3. Either one of the two Output Enable inputs being HIGH

will force I/O terminals to be in the off state. It is noted that

each I/O terminal is a three-state output and a CMOS

buffer input.

The CD54AC299/3A and CD54ACT299/3A are supplied in

20 lead dual-in-line ceramic packages (F suffix).

ACT INPUT LOAD TABLE

INPUT

UNIT LOAD (NOTE 1)

S1, S2, OE1, OE2

0.83

SL, CP

0.67

MR

1.33

NOTE:

1. Unit load is

∆I

Description

The CD54AC299/3A and CD54ACT299/3A are three-state,

8-input universal shift/storage registers with common parallel

I/O pins. These devices utilize the Harris Advanced CMOS

Logic technology. These registers have four synchronous

operating modes controlled by the two select inputs as shown

in the Mode Select (S0, S1) table. The Mode Select, the Serial

only to the LOW-to-HIGH transition of the clock pulse (CP).

S0, S1 and Data inputs must be present one setup time prior

to the positive transition of the clock.

The Master Reset (MR) is an asynchronous active-LOW

input. When MR is LOW, the register is cleared regardless of

the status of all other inputs. The register can be expanded

by cascading same units by tying the serial output (QO) to

the serial data (DS7) input of the preceding register, and

tying the serial output (Q7) to the serial data (DS0) input of

the following register. Recirculating the (n x 8) bits is accom-

plished by tying the Q7 of the last stage to the DS0 of the

first stage.

The three-state input/output (I/O) port has three modes of

operation

1. Both Output Enable (OE1 and OE2) inputs are LOW and

S0 or S1 or both are LOW, the data in the register is

present at the eight outputs.

June 1997

File Number

3907

Functional Diagram

12

2

3

9

THREE-STATE

CONTROL

18

11

10

I/O

THREE-STATE

OUTPUTS

I/O

THREE-STATE

OUTPUTS

SHIFT

REGISTER

MODE

SELECTION

7

6

5

4

8

1

20

13

14

15

16

17

19

Q7

S1

Q0

S0

GND

DS0

DS7

MR

OE2

OE1

CP

STANDARD OUTPUT

BUS LINE

OUTPUTS

STANDARD OUTPUT

BUS LINE

OUTPUTS

COMING SOON!

COMPLETE DATA SHEET