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AD7896 数据表(PDF) 3 Page - Analog Devices |
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AD7896 数据表(HTML) 3 Page - Analog Devices |
3 / 15 page AD7896 –3– Test Conditions/ Parameter A Version 1 B Version J Version S Version Unit Comments POWER REQUIREMENTS VDD 2.7/5.5 2.7/5.5 2.7/5.5 2.7/5.5 V min/max IDD 444 4 mA max Digital Input @ DGND, VDD = 2.7 V to 3.6 V 555 5 mA max Digital Inputs @ DGND, VDD = 5 V ± 10% Power Dissipation 10.8 10.8 10.8 10.8 mW max VDD = 2.7 V, Typically 9 mW Power-Down Mode Digital Inputs @ DGND IDD @ 25 °C 555 typ 5 µA max VDD = 2.7 V to 3.6 V TMIN to TMAX 15 15 75 75 µA max VDD = 2.7 V to 3.6 V IDD @ 25 °C50 5050 50 µA max VDD = 5 V ± 10% TMIN to TMAX 150 150 500 500 µA max VDD = 5 V ± 10% Power Dissipation @ 25 °C 13.5 13.5 13.5 13.5 µW max VDD = 2.7 V NOTES 1Temperature ranges are as follows: A, B Versions: –40 °C to +85°C; J Version: 0°C to +70°C; S Version: –55°C to +125°C. 2Applies to Mode 1 operation. See the section on Operating Modes. 3See Terminology. 4Sample tested @ 25 °C to ensure compliance. 5This 14 µs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for narrow CONVST pulsewidth the conversion time is effectively the wake-up time plus conversion time, hence 14 µs. This can be seen from Figure 3. Note that if the CONVST pulsewidth is greater than 6 µs, the effective conversion time will increase beyond 14 µs. Specifications subject to change without notice. Parameter A, B Versions J Version S Version Unit Test Conditions/Comments t1 40 40 40 ns min CONVST Pulsewidth t2 40 2 40 2 45 2 ns min SCLK High Pulsewidth t3 40 2 40 2 45 2 ns min SCLK Low Pulsewidth t4 Data Access Time after Falling Edge of SCLK 60 3 60 3 70 3 ns max VDD = 5 V ± 10% 100 3 100 3 110 3 ns max VDD = 2.7 V to 3.6 V t5 10 10 10 ns min Data Hold Time after Falling Edge of SCLK t6 50 4 50 4 50 4 ns max Bus Relinquish Time after Falling Edge of SCLK NOTES 1Sample tested at 25 °C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V DD) and timed from a voltage level of 1.4 V. 2The SCLK maximum frequency is 10 MHz. Care must be taken when interfacing to account for the data access time, t 4, and the setup time required for the user’s processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See Serial Interface section for more information. 3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2 V. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 6, quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. TIMING CHARACTERISTICS1 (VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V) 1.6V 1.6mA 400 A 50pF TO OUTPUT PIN Figure 1. Load Circuit for Access Time and Bus Relinquish Time Rev. D |
类似零件编号 - AD7896_15 |
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类似说明 - AD7896_15 |
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