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CD4000BMS 数据表(PDF) 1 Page - Intersil Corporation

部件名 CD4000BMS
功能描述  CMOS NOR Gate
Download  9 Pages
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

CD4000BMS 数据表(HTML) 1 Page - Intersil Corporation

  CD4000BMS Datasheet HTML 1Page - Intersil Corporation CD4000BMS Datasheet HTML 2Page - Intersil Corporation CD4000BMS Datasheet HTML 3Page - Intersil Corporation CD4000BMS Datasheet HTML 4Page - Intersil Corporation CD4000BMS Datasheet HTML 5Page - Intersil Corporation CD4000BMS Datasheet HTML 6Page - Intersil Corporation CD4000BMS Datasheet HTML 7Page - Intersil Corporation CD4000BMS Datasheet HTML 8Page - Intersil Corporation CD4000BMS Datasheet HTML 9Page - Intersil Corporation  
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7-649
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4000BMS, CD4001BMS
CD4002BMS, CD4025BMS
CMOS NOR Gate
Pinouts
CD4000BMS
TOP VIEW
CD4001BMS
TOP VIEW
CD4002BMS
TOP VIEW
CD4025BMS
TOP VIEW
NC
NC
A
B
C
H = A + B + C
VSS
VDD
F
E
D
K = D + E + F
L = G
G
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC = NO CONNECTION
A
B
J = A + B
K = C + D
C
D
VSS
VDD
H
G
M = G + H
L = E + F
F
E
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC = NO CONNECTION
J = A + B + C + D
A
B
C
D
NC
VSS
VDD
K = E + F + G + H
H
G
F
E
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC = NO CONNECTION
A
B
D
E
F
K = D + E + F
VSS
VDD
G
H
I
L = G + H + I
J = A + B + C
C
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC = NO CONNECTION
Features
• High-Voltage Types (20V Rating)
• Propagation Delay Time = 60ns (typ.) at CL = 50pF,
VDD = 10V
• Buffered Inputs and Outputs
• Standard Symmetrical Output Characteristics
• 100% Tested for Maximum Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1
µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Device’s
Description
CD4000BMS,
CD4001BMS,
CD4002BMS,
and
CD4025BMS NOR gates provide the system designer with
direct implementation of the NOR function and supplement
the existing family of CMOS gates. All inputs and outputs are
buffered.
The CD4000BMS, CD4001BMS, CD4002BMS and the
CD4025BMS is supplied in these 14 lead outline packages:
CD4000BMS
- Dual 3 Plus Inverter
CD4001BMS
- Quad 2 Input
CD4002BMS
- Dual 4 Input
CD4025BMS
- Triple 3 Input
CD4000B CD4001B CD4002B CD4025B
Braze Seal DIP
H4X
H4Q
H4Q
H4Q
Frit Seal DIP
H1B
H1B
H1B
H1B
Ceramic Flatpack
H3W
H3W
H3W
H3W
File Number
3289
November 1994


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