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CA3282 数据表(PDF) 3 Page - Intersil Corporation

部件名 CA3282
功能描述  Octal Low Side Power Driver with Serial Bus Control
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

CA3282 数据表(HTML) 3 Page - Intersil Corporation

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3
Output Three State Leakage
Current
IOL
VDD = 5.25V, 0 < VO < VDD,
CE Pin Held High
-10
-
+10
µA
Output Capacitance
COUT
0 < VO < VDD, CE Pin Held High
-
-
20
pF
Electrical Specifications
VDD = 5V, TA = -40
oC to 125oC, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Serial Peripheral Interface Timing
(See Figure 1B)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Frequency
fOPER
D.C.
Note 4
3.0
MHz
Enable Lead Time
(2)
tLEAD
-
<100
200
ns
Enable Lag Time
(3)
tLAG
-
<100
200
ns
Clock HIGH Time
(4)
twSCK
H
-
50
100
ns
Clock LOW Time
(5)
twSCK
L
-
50
100
ns
Data Setup Time
(6)
tSU
-20
50
ns
Data Hold Time
(7)
tH
-20
50
ns
Enable Time
(8)
tEN
-
50
100
ns
Disable Time
(9)
tDIS
-
150
300
ns
Data Valid Time
(10)
tV
-
75
150
ns
Output Data Hold Time
(11)
tHO
050
-
ns
Rise Time (MISO Output)
(12)
trSO
VDD = 20% to 70%, CL = 200pF
-
35
100
ns
Rise Time SPI Inputs (SCK, MOSI, CE)
(12)
trSI
VDD = 20% to 70%, CL = 200pF
-
-
50
ns
Fall Time (MISO Output)
(13)
tfSO
VDD = 70% to 20%, CL = 200pF
-
45
100
ns
Fall Time SPI Inputs (SCK, MOSI, CE)
(13)
tfSI
VDD = 70% to 20%, CL = 200pF
-
-
50
ns
NOTES:
3. Refer to Figure 4A for IOUT current vs VSAT voltage. Typical rDS(ON) values are given for -40
oC, 25oC, 105oC and 125oC temperatures.
4. The Maximum Operating Frequency is typically greater than 10MHz but it is application limited primarily by external SPI input rise/fall
times and MISO output loading.
Timing Diagrams
FIGURE 1A. DATA AND CLOCK TIMING DIAGRAM
CE
SCK
MSB
6
5
4
3
2
1
LSB
(CPOL = 0, CPHA = 1)
INTERNAL STROBE FOR DATA CAPTURE
CA3282


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