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AD7440 数据表(PDF) 10 Page - Analog Devices |
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AD7440 数据表(HTML) 10 Page - Analog Devices |
10 / 29 page AD7440/AD7450A Rev. C | Page 9 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VREF VIN+ VIN– GND 8 7 6 5 VDD 1 SCLK 2 SDATA 3 CS 4 AD7440/ AD7450A TOP VIEW (Not to Scale) Figure 5. Pin Configuration for 8-Lead SOT-23 VDD SCLK SDATA CS 8 7 6 5 VREF 1 VIN+ 2 VIN– 3 GND 4 AD7440/ AD7450A TOP VIEW (Not to Scale) Figure 6. Pin Configuration for 8-Lead MSOP Table 5. Pin Function Descriptions Mnemonic Function VREF Reference Input for the AD7440/AD7450A. An external reference must be applied to this input. For a 5 V power supply, the reference is 2.5 V (±1%) for specified performance. For a 3 V power supply, the reference is 2 V (±1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1 μF. See the Reference section for more details. VIN+ Positive Terminal for Differential Analog Input. VIN– Negative Terminal for Differential Analog Input. GND Analog Ground. Ground reference point for all circuitry on the AD7440/AD7450A. All analog input signals and any external reference signal should be referred to this GND voltage. CS Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7440/AD7450A and framing the serial data transfer. SDATA Serial Data. Logic output. The conversion result from the AD7440/AD7450A is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7450A consists of four leading zeros followed by the 12 bits of conversion data, which are provided MSB first; the data stream of the AD7440 consists of four leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros. In both cases, the output coding is twos complement. SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process. VDD Power Supply Input. VDD is 3 V (+20%/–10%) or 5 V (±5%). This supply should be decoupled to GND with a 0.1 μF capacitor and a 10 μF tantalum capacitor in parallel. |
类似零件编号 - AD7440_15 |
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类似说明 - AD7440_15 |
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