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AD7397 数据表(PDF) 1 Page - Analog Devices |
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AD7397 数据表(HTML) 1 Page - Analog Devices |
1 / 12 page REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD7396/AD7397 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 3 V, Parallel Input Dual 12-Bit /10-Bit DACs FUNCTIONAL BLOCK DIAGRAM DACA REGISTER 12 INPUTA REGISTER DACB REGISTER 12 INPUTB REGISTER AD7396 12-BIT DACA 12-BIT DACB 1 DATA LDA CS A/ B DGND RS SHDN VDD VOUTA VREF VOUTB AGND LDB 12 FEATURES Micropower: 100 A/DAC 0.1 A Typical Power Shutdown Single Supply +2.7 V to +5.5 V Operation Compact 1.1 mm Height TSSOP 24-Lead Package AD7396: 12-Bit Resolution AD7397: 10-Bit Resolution 0.9 LSB Differential Nonlinearity Error APPLICATIONS Automotive Output Span Voltage Portable Communications Digitally Controlled Calibration PC Peripherals GENERAL DESCRIPTION The AD7396/AD7397 series of dual, 12-bit and 10-bit voltage- output digital-to-analog converters are designed to operate from a single +3 V supply. Built using a CBCMOS process, these monolithic DACs offer the user low cost and ease of use in single supply +3 V systems. Operation is guaranteed over the supply voltage range of +2.7 V to +5.5 V, making this device ideal for battery operated applications. A 12-bit wide data latch loads with a 45 ns write time allowing interface to fast processors without wait states. The double buffered input structure allows the user to load the input registers one at a time, then a single load strobe tied to both LDA+LDB inputs will simultaneously update both DAC out- puts. LDA and LDB can also be independently activated to immediately update their respective DAC registers. An address input (A/ B) decodes DACA or DACB when the chip select CS input is strobed. Additionally, an asynchronous RS input sets the output to zero-scale at power on or upon user demand. Power shutdown to submicroamp levels is directly controlled by the active low SHDN pin. While in the power shutdown state register data can still be changed even though the output buffer is in an open circuit state. Upon return to the normal operating state the latest data loaded in the DAC register will establish the output voltage. Both parts are offered in the same pinout, allowing users to select the amount of resolution appropriate for their applications without circuit card changes. The AD7396/AD7397 are specified for operation over the ex- tended industrial (–40 °C to +85°C) temperature range. The AD7397AR is specified for the –40 °C to +125°C automotive temperature range. AD7396/AD7397s are available in plastic DIP, and 24-lead SOIC packages. The AD7397ARU is avail- able for ultracompact applications in a thin 1.1 mm height TSSOP 24-lead package. CODE – Decimal 1.0 0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 512 1024 1536 2048 2560 3072 3584 4096 VDD = +3V VREF = +2.5V TA = +25 C, +85 C, –55 C SUPERIMPOSED Figure 1. DNL vs. Digital Code at Temperature |
类似零件编号 - AD7397_15 |
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类似说明 - AD7397_15 |
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