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AD6636 数据表(PDF) 9 Page - Analog Devices |
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AD6636 数据表(HTML) 9 Page - Analog Devices |
9 / 80 page AD6636 Rev. A | Page 9 of 80 SERIAL PORT TIMING CHARACTERISTICS1, , 2 3 Table 5. Parameter Temp Test Level Min Typ Max Unit SERIAL PORT CLOCK TIMING REQUIREMENTS tSCLK SCLK Period Full IV 10.0 ns tSCLKL SCLK Low Time Full IV 1.60 0.5 × tSCLK ns tSCLKH SCLK High Time Full IV 1.60 0.5 × tSCLK ns SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0) tSSDI SDI to ↑SCLK Setup Time Full IV 1.30 ns tHSDI SDI to ↑SCLK Hold Time Full IV 0.40 ns tSSCS SCS to ↑SCLK Setup Time Full IV 4.12 ns tHSCS SCS to ↑SCLK Hold Time Full IV −2.78 ns tDSDO ↑SCLK to SDO Delay Time Full IV 4.28 7.96 ns SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1) tSSDI SDI to ↑SCLK Setup Time Full IV 0.80 ns tHSDI SDI to ↑SCLK Hold Time Full IV 0.40 ns tSSRFS SRFS to ↓SCLK Setup Time Full IV 1.60 ns tHSRFS SRFS to ↓SCLK Hold Time Full IV −0.13 ns tSSTFS STFS to ↓SCLK Setup Time Full IV 1.60 ns tHSTFS STFS to ↑SCLK Hold Time Full IV −0.30 ns tSSCS SCS to ↑SCLK Setup Time Full IV 4.12 ns tHSCS SCS to ↑SCLK Hold Time Full IV −2.76 ns tDSDO ↑SCLK to SDO Delay Time Full IV 4.29 7.95 ns 1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V. 2 CLOAD = 40 pF on all outputs, unless otherwise noted. 3 SCLK rise/fall time should be 3 ns maximum. EXPLANATION OF TEST LEVELS FOR SPECIFICATIONS Table 6. Test Level Description I 100% production tested. II 100% production tested at 25°C, and sample tested at specified temperatures. III Sample tested only. IV Parameter guaranteed by design and analysis. V Parameter is typical value only. VI 100% production tested at 25°C, and sampled tested at temperature extremes. |
类似零件编号 - AD6636_15 |
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类似说明 - AD6636_15 |
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