AD6411

–6–

REV. 0

The block diagram shows the principle of operation of these two

modes together with the internal switch settings as shown in

Figure 2.

Table I. Supported Demodulation Modes

Mode

SW1

SW2

SW3

Comment

Prior to RX

Open

Closed Closed Precharge Loop

SFS = Don’t Care

Filter and C Offset

SFM = 0

Capacitor

Normal Demod –

Open

Closed Open

Use Temperature

Active RX

Compensated

SFS = Don’t Care

Reference Voltage

SFM = 0

S-Field Sample

Closed Open

Open

SFS = 1

SFM = 1

S-Field Hold

Open

Open

Open

SFS = 0

SFM = 1

An important consideration in normal demodulation mode is

any drift after the initial setup of the VCO. One mechanism is

the Capacitance vs. Temperature coefficient of the external

varactor. This has a known characteristic which is compensated

by an internal reference voltage generation circuit.

UHF VCO

A single UHF VCO oscillator is provided operating at one-half

the required frequency. Therefore, in transmit mode the

oscillator operates from (approximately) 940 MHz to 950 MHz,

and in receive mode the oscillator operates from (approxi-

mately) 884 MHz–895 MHz. This requires a switched resona-

tor design, and band switch control is provided by the AD6411.

A balanced oscillator configuration is used which has the advan-

tages of rejection of common-mode interference and noise, and

less coupling to and from other parts of the IC and radio.

Transmit Functions

The DECT transmit function is achieved by direct modulation

of the UHF VCO operating at half the final transmit output

frequency. An on-chip doubler converts this to the final carrier

frequency. In this mode the synthesizer is set to a high imped-

ance mode i.e., “fly-wheeled.” The drift is sufficiently low for

both single-slot and double-slot transmit operation.

Synthesizer and LO Functions

A complete synthesizer is implemented on the IC that is capable

of generating all the required DECT channel allocations (in-

cluding the extended DECT bands). This synthesizer can use

reference frequencies of either 13.824 MHz or 10.368 MHz,

controlled by the RD bit in the control register.

Synthesizer Programming

The required channels are programmed by setting the RD bit in

the control register to the correct value, then programming the

A and M Counters as shown below through the serial interface.

VCC

150nH

IFVCO

IF/110.592MHz

TC1

8pF

6.8pF

1k

ZC830

DATA FILTER

LOOP

FILTER

IFCP

96.768MHz

13.824MHz

GM1

IFLF

SW3

SW2

GM2

SW1

GM3

DMR

VREF

DEMOD DATA

COFF

VARACTOR

TEMP Co

COMPENSATION

AD6411

VREF

Figure 2. PLL Demodulator Block Diagram