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AD5533B 数据表(PDF) 8 Page - Analog Devices |
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AD5533B 数据表(HTML) 8 Page - Analog Devices |
8 / 16 page REV. A –8– AD5533B PIN FUNCTION DESCRIPTIONS Pin Function AGND (1–2) Analog GND Pins AVCC (1–2) Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. VDD (1–4) VDD Supply Pins. Voltage range from 8 V to 16.5 V. VSS (1–4) VSS Supply Pins. Voltage range from –4.75 V to –16.5 V. DGND Digital GND Pins DVCC Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. DAC_GND (1–2) Reference GND Supply for all the DACs REF_IN Reference Voltage for Channels 0–31 REF_OUT Reference Output Voltage VOUT (0–31) Analog Output Voltages from the 32 Channels VIN Analog Input Voltage A4–A1 1, A02 Parallel Interface. 5-address pins for 32 channels. A4 = MSB of channel address. A0 = LSB. CAL 1 Parallel Interface. Control input that allows all 32 channels to acquire VIN simultaneously. CS/SYNC This pin is both the active low chip select pin for the parallel interface and the frame synchronization pin for the serial interface. WR1 Parallel Interface. Write pin. Active low. This is used in conjunction with the CS pin to address the device using the parallel interface. OFFSET_SEL 1 Parallel Interface. Offset select pin. Active high. This is used to select the offset channel. SCLK 2 Serial Clock Input for Serial Interface. This operates at clock speeds up to 20 MHz. DIN 2 Data Input for Serial Interface. Data must be valid on the falling edge of SCLK. DOUT Output from the DAC Registers for Readback. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. SER/ PAR1 This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low, the parallel interface will be used. If it is tied high, the serial interface will be used. OFFS_IN Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the user wants to drive this pin with the offset channel. OFFS_OUT Offset Output. This is the acquired/programmed offset voltage that can be tied to the OFFS_IN pin to offset the span. BUSY This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when the acquisition operation is complete. TRACK/RESET2 If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the gain/offset stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge of TRACK. See TRACK Input section for further information. This input can also be used as a means of resetting the complete device to its power-on-reset conditions. This is achieved by applying a low going pulse of between 90 ns and 200 ns to this pin. See section on RESET Function for further details. NOTES 1Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition. 2Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition. |
类似零件编号 - AD5533B_15 |
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类似说明 - AD5533B_15 |
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