FC80960HT75SL2GT datasheet(10/102 Pages) INTEL

部件名	FC80960HT75SL2GT

功能描述	80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

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制造商	INTEL [Intel Corporation]

网页	http://www.intel.com

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80960HA/HD/HT

4

Advance Information Datasheet

2.2.6

Dual Programmable Timers

The processor provides two independent 32-bit timers, with four programmable clock rates. The

user configures the timers via the Timer Unit registers. These registers are memory-mapped within

the 80960Hx, addressable on 32-bit boundaries. The timers have a single-shot mode and

auto-reload capabilities for continuous operation. Each timer has an independent interrupt request

to the processor’s interrupt controller.

2.2.7

Processor Self Test

When a system error is detected, the FAIL pin is asserted, a fail code message is driven onto the

address bus, and the processor stops execution at the point of failure. The only way to resume

normal operation is to perform a RESET operation. Because System Error generation can occur

sometime after the bus confidence test and even after initialization during normal processor

operation, the FAIL pin is HIGH (logic “1”) before the detection of a System Error.

The processor uses only one read bus-transaction to signal the fail code message; the address of the

bus transaction is the fail code itself. The fail code is of the form: 0xfeffffnn; bits 6 to 0 contain a

mask recording the possible failures. Bit 7, when set to 1, indicates that the mask contains failures

from the internal Built-In Self-Test (BIST); when 0, the mask indicates other failures.

Ignore reserved bits 0 and 1. Also ignore bits 5 and 6 when bit 7 is clear (=0).

The mask is shown in Table 2 and Table 3.

Table 2.

Fail Codes For BIST (bit 7 = 1)

Bit

When Set:

6

On-chip Data-RAM failure detected by BIST.

5

Internal Microcode ROM failure detected by BIST.

4

Instruction cache failure detected by BIST.

3

Data cache failure detected by BIST.

2

Local-register cache or processor core failure detected by BIST.

1

Reserved. Always zero.

0

Reserved. Always zero.

Table 3.

Remaining Fail Codes (bit 7 = 0)

Bit

When Set:

6

Reserved. Always one.

5

Reserved. Always one.

4

A data structure within the IMI is not aligned to a word boundary.

3

A System Error during normal operation has occurred.

2

The Bus Confidence test has failed.

1

Reserved. Always zero.

0

Reserved. Always zero.

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