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AD5231BRUZ10 数据表(PDF) 5 Page - Analog Devices

部件名 AD5231BRUZ10
功能描述  Nonvolatile Memory, 1024-Position Digital Potentiometer
Download  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5231BRUZ10 数据表(HTML) 5 Page - Analog Devices

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Data Sheet
AD5231
Rev. D | Page 5 of 28
TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
INTERFACE TIMING CHARACTERISTICS2, 3
Clock Cycle Time (tCYC)
t1
20
ns
CS Setup Time
t2
10
ns
CLK Shutdown Time to CS Rise
t3
1
tCYC
Input Clock Pulse Width
t4, t5
Clock level high or low
10
ns
Data Setup Time
t6
From positive CLK transition
5
ns
Data Hold Time
t7
From positive CLK transition
5
ns
CS to SDO-SPI Line Acquire
t8
40
ns
CS to SDO-SPI Line Release
t9
50
ns
CLK to SDO Propagation Delay4
t10
RP = 2.2 kΩ, CL < 20 pF
50
ns
CLK to SDO Data Hold Time
t11
RP = 2.2 kΩ, CL < 20 pF
0
ns
CS High Pulse Width5
t12
10
ns
CS High to CS High5
t13
4
tCYC
RDY Rise to CS Fall
t14
0
ns
CS Rise to RDY Fall Time
t15
0.1
0.15
ms
Store/Read EEMEM Time6
t16
Applies to instructions 0x2, 0x3, and 0x9
25
ms
Power-On EEMEM Restore Time
tEEMEM1
RAB = 10 kΩ
140
μs
Dynamic EEMEM Restore Time
tEEMEM2
RAB = 10 kΩ
140
μs
WP High or Low to CS Fall Time
t
WP
40
ns
CS Rise to Clock Rise/Fall Setup
t17
10
ns
Preset Pulse Width (Asynchronous)
tPRW
Not shown in timing diagram
50
ns
Preset Response Time to Wiper Setting
tPRESP
PR pulsed low to refresh wiper positions
70
μs
FLASH/EE MEMORY RELIABILITY
Endurance7
100
kCycles
Data Retention8
100
Years
1 Typical values represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test.
3 See timing diagrams (Figure 3 and Figure 4) for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed
from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 35 V.
4 Propagation delay depends on the value of VDD, RPULL-UP, and CL.
5 Valid for commands that do not activate the RDY pin.
6 RDY pin low only for Instructions 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_2, 3 ~ 20 ms; CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.12 ms. Device operation at TA = −40°C and
VDD < 3 V extends the EEMEM store time to 35 ms.
7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
8 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.


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