IA6805E2

Data Sheet

Microprocessor Unit

As of Production Version 00

Copyright

© 2002

ENG21108140100

www.innovasic.com

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Description

The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a

CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The

following paragraphs will further describe this system block diagram and design in more detail.

PROGRAM

COUNTER

LOW

112x8

RAM

ADDRESS

DRIVE

MUX

BUS

DRIVE

CPU

PORT

A

REG

OSCILLATOR

DATA

DIR

REG

PORT

B

REG

DATA

DIR

REG

CPU

CONTROL

ALU

BUS

CONTROL

STACK

POINTER

CONDITION

CODE

REGISTER

INDEX

REGISTER

ACCUMULATOR

PROGRAM

COUNTER

HIGH

TIMER CONTROL

PRESCALER

TIMER/

COUNTER

PA0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PB0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PA0

OSC1

OSC2

TIMER

RESET_N

LI

IRQ_N

B0

B7

B6

B5

B4

B3

B2

B1

A8

A12

A11

A10

A9

RW_N

DS

AS

8

A

5

6

5

8

8

X

CC

SP

PCH

PCL

PORT

A

I/O

LINES

PORT

B

I/O

LINES

MULTIPLEXED

ADDRESS

DATA

BUS

ADDRESS

BUS

ADDRESS STROBE

DATA STROBE

READ/WRITE

Figure 1. System Block Diagram