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AD1833 数据表(PDF) 10 Page - Analog Devices |
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AD1833 数据表(HTML) 10 Page - Analog Devices |
10 / 20 page REV. A AD1833 –10– FUNCTIONAL DESCRIPTION Device Architecture The AD1833 is a six-channel audio DAC featuring multibit sigma-delta ( S-D) technology. The AD1833 features three stereo converters (providing six channels); each stereo channel is con- trolled by a common bit-clock (BCLK) and synchronization signal (L/RCLK). General Overview The AD1833 is designed to run with an internal MCLK (IMCLK) of 24.576 MHz and a modulator rate of 6.144 MHz (i.e., IMCLK/4). From this IMCLK frequency, sample rates of 48 kHz and 96 kHz can be achieved on six channels or 192 kHz can be achieved on two channels. The internal clock should never be run at a higher frequency but may be reduced to achieve lower sampling rates, i.e., for a sample rate of 44.1 kHz, the appro- priate internal MCLK is 22.5792 MHz. The modulator rate scales in proportion with the MCLK scaling. Interpolator The interpolator consists of as many as three stages of sample rate doubling and half-band filtering followed by a 16-sample zero order hold (ZOH). The sample rate doubling is achieved by zero stuffing the input samples, and a digital half-band filter is used to remove any images above the band of interest and to bring the zero samples to their correct values. The interpolator output must always be at a rate of IMCLK/64. Depending on the interpolation rates selected, one, two, or all three stages of doubling may be switched in. This allows for three different sample rate inputs for any given IMCLK. For an IMCLK of 24.576 MHz, all three doubling stages are used with a 48 kHz input sample rate; with a 96 kHz input sample rate, only two doubling stages are used; and with a 192 kHz input sample rate, only one doubling stage is used. In each case, the input sample frequency is increased to 384 kHz (IMCLK/64). The ZOH holds the interpolator samples for upsampling by the modulator. This is done at a rate 16 times the interpolator output sample rate. Modulator The modulator is a 6-bit, second order implementation and uses data scrambling techniques to achieve perfect linearity. The modu- lator samples the output of the interpolator stage(s) at a rate of (IMCLK/4). OPERATING FEATURES SPI Register Definitions The SPI port allows flexible control of the device’s programmable functions. It is organized around nine registers: six individual channel volume registers and three control registers. Each write operation to the AD1833 SPI control port requires 16 bits of serial data in MSB-first format. The four most significant bits are used to select one of nine registers (seven register addresses are reserved), and the bottom 10 bits are written to that register. This allows a write to one of the nine registers in a single 16-bit transaction. The SPI CCLK signal is used to clock in the data. The incoming data should change on the falling edge of this signal and remain valid during the rising edge. At the end of the 16 CCLK periods, the CLATCH signal should rise to latch the data internally into the AD1833 (see Figure 2). The serial interface format used on the control port uses a 16-bit serial word, as shown in Table I. The 16-bit word is divided into several fields: Bits 15 through 12 define the register address, Bits 11 and 10 are reserved and must be programmed to 0, and Bits 9 through 0 are the data field (which has specific definitions, depending on the register selected). Table I. Control Port Map Register Address Reserved 1 Data Field 15 2 14 13 12 11 10 9876543210 NOTES 1Must be programmed to zero. 2Bit 15 = MSB. Bit 15 Bit 14 Bit 13 Bit 12 Register Function 0 000 DAC Control 1 0 001 DAC Control 2 0 010 DAC Volume 1 0 011 DAC Volume 2 0 100 DAC Volume 3 0 101 DAC Volume 4 0 110 DAC Volume 5 0 111 DAC Volume 6 1 000 DAC Control 3 1 001 Reserved 1 010 Reserved 1 011 Reserved 1 100 Reserved 1 101 Reserved 1 110 Reserved 1 111 Reserved |
类似零件编号 - AD1833_15 |
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类似说明 - AD1833_15 |
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