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ILC5062AM-28 数据表(PDF) 3 Page - Impala Linear Corporation

部件名 ILC5062AM-28
功能描述  ST-23 POWER SUPPLY RESET MONITOR WITH COMPLEMENTARY CMOS OUTPUT
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制造商  IMPALA [Impala Linear Corporation]
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标志 IMPALA - Impala Linear Corporation

ILC5062AM-28 数据表(HTML) 3 Page - Impala Linear Corporation

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The following designators 1~6 refer to the timing diagram below.
1. While the input voltage (VIN) is higher than the detect
voltage (VDF), the output voltage at VOUT pin equals the
input voltage at VIN pin.
2. When the input VIN voltage falls lower than VDF, VOUT
drops near ground voltage.
3. If the input voltage decreases below the minimum operat-
ing voltage (VMIN), the VOUT output voltage will be undefined.
4. During an increase of the input voltage from the VSS
voltage, VOUT is undefined at the voltage below VMIN.
Exceeding the VMIN level, the ouput stays at the ground
level (VSS) between the minimum operating voltage (VMIN)
and the detect release voltage (VDR).
5. If the input voltage increases more than VDR, the output
voltage at VOUT pin equals the input voltage at VIN pin.
6. The difference between VDR and VDF is the hysteresis
in the system.
6
5
4
3
1
2
INPUT VOLTAGE (V
IN)
DETECT RELEASE VOLTAGE (V
DR)
DETECT FAIL VOLTAGE (V
DF)
MINIMUM OPERATING VOLTAGE (V
MIN)
GROUND VOLTAGE (V
SS)
OUTPUT VOLTAGE (V
OUT)
GROUND VOLTAGE (V
SS)
SOT-23 Power Supply reset Monitor With Complementary CMOS Output
Impala Linear Corporation
3
(408) 574-3939
www.impalalinear.com
June 1999
ILC5062 1.3
Functional Description
Timing Diagram


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