AD1380

Rev. D | Page 9 of 12

CALIBRATION (14-BIT RESOLUTION EXAMPLES)

External zero adjustment and gain adjustment potentiometers,

connected as shown in Figure 3 and Figure 4, are used for

device calibration. To prevent interaction of these two

adjustments, zero is always adjusted first and then gain. Zero is

adjusted with the analog input near the most negative end of the

analog range (0 for unipolar and minus full scale for bipolar

input ranges). Gain is adjusted with the analog input near the

most positive end of the analog range.

0 V to +10 V Range

Set analog input to +1 LSB

B

14

= 0.00061 V; adjust zero for digital

output = 11111111111110. Zero is now calibrated. Set analog

input to +FSR − 2 LSB = +9.99878 V; adjust gain for

00000000000001 digital output code; full scale (gain) is now

calibrated. Half-scale calibration check: set analog input to

5.00000 V; digital output code should be 01111111111111.

−10 V to +10 V Range

Set analog input to −9.99878 V; adjust zero for 1111111111110

digital output (complementary offset binary) code. Set analog

input to 9.99756 V; adjust gain for 00000000000001 digital

output (complementary offset binary) code. Half-scale

calibration check: set analog input to 0.00000 V; digital output

(complementary offset binary) code should be 01111111111111.

Other Ranges

Representative digital coding for 0 V to +10 V and −10 V to

+10 V ranges is given in the 0 V to +10 V Range section and

−10 V to +10 V Range section. Coding relationships and

calibration points for 0 V to +5 V, −2.5 V to +2.5 V and −5 V to

+5 V ranges can be found by halving proportionally the

corresponding code equivalents listed for the 0 V to +10 V and

−10 V to +10 V ranges, respectively, as indicated in Table 4.

Zero and full-scale calibration can be accomplished to a

precision of approximately ±1/2 LSB using the static adjustment

procedure described above. By summing a small sine or

triangular wave voltage with the signal applied to the analog

input, the output can be cycled through each of the calibration

codes of interest to more accurately determine the center (or

end points) of each discrete quantization level. A detailed

description of this dynamic calibration technique is presented

in Analog-Digital Conversion Handbook, edited by D. H.

Sheingold, Prentice-Hall, Inc., 1986.

GROUNDING, DECOUPLING AND LAYOUT

CONSIDERATIONS

Many data acquisition components have two or more ground

pins that are not connected together within the device. These

grounds are usually referred to as the DIGITAL COMMON

(logic power return), ANALOG COMMON (analog power

return), or analog signal ground. These grounds (Pin 8 and

Pin 30) must be tied together at one point as close as possible to

the converter. Ideally, a single solid analog ground plane under

the converter would be desirable. Current flows through the

wires and etch stripes on the circuit cards and, since these paths

have resistance and inductance, hundreds of millivolts can be

generated between the system analog ground point and the

ground pins of the AD1380. Separate wide conductor stripe

ground returns should be provided for high resolution

converters to minimize noise and IR losses from the current

flow in the path from the converter to the system ground point.

In this way, AD1380 supply currents and other digital logic-gate

return currents are not summed into the same return path as

analog signals where they would cause measurement errors.

Each of the AD1380 supply terminals should be capacitively

decoupled as close to the AD1380 as possible. A large value

(such as 1 μF) capacitor in parallel with a 0.1 μF capacitor is

usually sufficient. Analog supplies are to be bypassed to the

ANALOG COMMON (analog power return) Pin 30 and the

logic supply is bypassed to DIGITAL COMMON (logic power

return) Pin 8.

The metal cover is internally grounded with respect to the

power supplies, grounds and electrical signals. Do not

externally ground the cover.