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AD807 数据表(PDF) 2 Page - Analog Devices

部件名 AD807
功能描述  Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
Download  12 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD807 数据表(HTML) 2 Page - Analog Devices

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REV. B
–2–
AD807–SPECIFICATIONS
Parameter
Condition
Min
Typ
Max
Unit
QUANTIZER–DC CHARACTERISTICS
Input Voltage Range
@ PIN or NIN
2.5
VCC
V
Input Sensitivity, VSENSE
PIN–NIN, Figure 1, BER =
≤ 1 × 10–10
2mV
Input Overdrive, VOD
Figure 1, BER =
≤ 1 × 10–10
0.001
2.5
V
Input Offset Voltage
50
500
µV
Input Current
510
µA
Input RMS Noise
BER =
≤ 1 × 10–10
50
µV
Input Peak-to-Peak Noise
BER =
≤ 1 × 10–10
650
µV
QUANTIZER–AC CHARACTERISTICS
Upper –3 dB Bandwidth
180
MHz
Input Resistance
1M
Input Capacitance
2pF
Pulsewidth Distortion
100
ps
LEVEL DETECT
Level Detect Range
RTHRESH = INFINITE
0.8
2
4.0
mV
RTHRESH = 49.9 k
4
5
7.4
mV
RTHRESH = 3.4 k
14
20
25
mV
Response Time
DC-Coupled
0.1
1.5
µs
Hysteresis (Electrical)
RTHRESH = INFINITE
2.3
4.0
10.0
dB
RTHRESH = 49.9 k
3.0
5.0
9.0
dB
RTHRESH = 3.4 k
3.0
7.0
10.0
dB
SDOUT Output Logic High
Load = +4 mA
3.6
V
SDOUT Output Logic Low
Load = –1.2 mA
0.4
V
PHASE-LOCKED LOOP NOMINAL
CENTER FREQUENCY
155.52
MHz
CAPTURE RANGE
155
156
MHz
TRACKING RANGE
155
156
MHz
STATIC PHASE ERROR
2
7–1 PRN Sequence
4
20
Degrees
SETUP TIME (tSU)
Figure 2
3.0
3.2
3.5
ns
HOLD TIME (tH)
Figure 2
3.0
3.1
3.3
ns
PHASE DRIFT
240 Bits, No Transitions
40
Degrees
JITTER
2
7–1 PRN Sequence
2.0
Degrees RMS
2
23–1 PRN Sequence
2.0
2.7
Degrees RMS
JITTER TOLERANCE
f = 10 Hz
3000
Unit Intervals
f = 6.5 kHz
4.5
7.6
Unit Intervals
f = 65 kHz
0.45
1.0
Unit Intervals
f = 1.3 MHz
0.45
0.67
Unit Intervals
JITTER TRANSFER
Peaking (Figure 11)
CD = 0.15
µF
0.08
dB
CD = 0.33
µF
0.04
dB
Bandwidth
65
92
130
kHz
Acquisition Time
CD = 0.1
µF223–1 PRN Sequence, T
A = 25
°C4 × 105
2
× 106
Bit Periods
CD = 0.33
µFV
CC = 5 V, VEE = GND
2
× 106
Bit Periods
POWER SUPPLY VOLTAGE
VMIN to VMAX
4.5
5.5
Volts
POWER SUPPLY CURRENT
VCC = 5.0 V, VEE = GND, TA = 25
°C
25
34.5
39.5
mA
PECL OUTPUT VOLTAGE LEVELS
Output Logic High, VOH
VCC = 5.0 V, VEE = GND, TA = 25
°C
–1.2
–1.0
–0.7
Volts
Output Logic Low, VOL
Referenced to VCC
–2.0
–1.8
–1.7
Volts
SYMMETRY (Duty Cycle)
ρ = 1/2, T
A = 25
°C,
Recovered Clock Output, Pin 5
VCC = 5 V, VEE = GND
50.1
54.1
%
OUTPUT RISE / FALL TIMES
Rise Time (tR)
20%–80%
1.1
1.5
ns
Fall Time (tF)
80%–20%
1.1
1.5
ns
Specifications subject to change without notice.
(TA = TMIN to TMAX, VCC = VMIN to VMAX, CD = 0.1 F, unless otherwise noted.)


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